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You do this by constructing a loop and adding up the individual instruction times and multiplying by the loop count, offsetting the end of loop and overhead.

For example, in the 8085, running at a 3 MHz clock (6 MHZ crystal) with no wait states, and a desired 1 ms delay...

PUSH PSW ; 12

MVI A,212 ; 7

LOOP DCR A ; 4

JNZ LOOP ; 7/10

NOP; 4

POP PSW ; 12

The numbers in the comments are the clock cycles for the instructions, assuming no wait states. (If you had wait states, you would need to incorporate them.) At 3 MHz, 1 ms is 3000 clocks. Overhead is 32 clocks, 35 - 3 for the last iteration of the loop. That leaves 2972 clocks. Divide that by 14, the loop time, and you get a loop count of 212. The total time will be 32 + 212 * 14, or 3000 clocks. The NOP instruction compensates for the fact that the actual total time without it would be 2996 clocks.

If you need more time, you add more "busy" time inside the loop, or make nested loops. Better, because this does not compensate for other processing time, is to setup an external counter and feed it into an interrupt, perhaps RST7.5, at the desired frequency.

As far as the 8086/8088, I cannot answer, because I am not intimate with that processor. As far as higher incarnations of processors, that is even harder because latency and cache hit/miss ratios inter into the equation, but you get the picture with this example.

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