3 T states for instruction fetch, 1 T state for decode, 1 T state for register E decrement, 1 T state for possible register D decrement.
DCX D means decrement register pair DE by one
Because that is the way Intel designed the INX instruction of the 8085. The 8080 is also the same. INX increments (and DCX decrements) the 16 bit register pairs or BC, DE or HL, depending on what register pair you specify in the INX (or DCX) instruction. To check is the value is 0 after an INX (or DCX) instruction, you need to OR the values of the register pair into the A register. For example..... INX H ;increment HL register pair MOV A,H ; move H register into the accumulator ORA L ; Logical OR it with the L register JZ ADDR ; If 0 then jump to ADDR
no....it does not aff
610 is DCX
It is: DCX = 610
DCX = 610
DCX (500+100+10 = 610)
DCX (610)
I would consider: NO!
Lxi b, 0000h lhld 8000h xchg lhld 8002h dcx d l006: lda 8002h add l mov l, a lda 8003h adc h mov h, a jnc l013 l013: inx b dcx d mov a, d ora e jnz l006 shld 8006h mov l, c mov h, b shld 8004h hlt
DCX
Write a Subroutine for 8085 to generate delay 0f 10ms(assume .333us clock cycle); REQUIRED T STATES; = 10ms/.333us; = 30030 T STATES; SO WE CAN SAY VALUE OF COUNT HERE WILL BE HIGH; THEREFORE TAKING A REGISTER PAIR AS A COUNTERLXI B, COUNT ; 10T LOWER ADDRESS IN B HIGHER IN CL1 DCX B ; 6TMOV A,B ; 4T MOVE LOWER ADDRESS IN AORA C ; 4T SEE IF BOTH A AND C ARE ZEROJNZ L1 ; 10/7TRET ; 10T; Td = 10 + COUNT X ( 6 + 4 + 4 + 10) + 10 - 3 = 30030; 24COUNT = 30030 - 17 = 30013; COUNT = 1250(DEC) = 04E2(HEX)