masking of interrupts is the temporal disabling of the current code the processor is executing to let higher priority ISRs (interrupt Services Routine) to be executed.
Finishes the current executing instruction and then serves the interrupt.
The BIOS function in the 8086 microprocessor is called an interrupt function. It is an interrupt function because it is not called by a function call instruction.
The lowest priority interrupt in the 8085 microprocessor is INTR, unless you also consider the software interrupts, RST 0 through RST 7, which are even lower.
Interrupt Acknowledgegenerated by the microprocessor in response to INTR. Causes the interrupt vector to be put onto the data bus
RIM is Read Interrupt Mask. It is used to access the interrupt mask register, which contains the status of the three interrupt masks and the serial input data pin.
The highest priority interrupt in a microprocessor is usually the reset interrupt. When a reset occurs, the microprocessor is forced to stop its current operations and begin executing the reset routine. This is critical for initializing the processor and setting it to a known state before starting normal operations.
The 5.5 in RST 5.5 means that the interrupt vector is located between RST 5 and RST 6.
An Interrupt is a signal that goes into a microprocessor that tells it something has happened that needs attention. There are generally dedicated pins on the microprocessor, often called "Int" (for Interrupt) and "NMI" (for Non-Maskable Interrupt). For a microprocessor, an interrupt signal is like the bell on a telephone is for you; it's a notice that you should stop what you are doing now and deal with this issue that has come up. Exact procedures for dealing with an interrupt vary from one microprocessor to another; generally, the microprocessor puts out a signal that says "Where should I go, then?" and a piece of hardware, the Interrupt Controller, then responds with a signal that tells it which condition has happened. The processor then starts processing the indicated piece of code, and that piece of code handles the condition. The Interrupt Controller often handles setting priority for interrupts, accepting a number of signals (often four), and setting priorities on each. It will trigger another interrupt in the middle of processing one if the new interrupt is a higher priority than the one that is already being processed, or will hold on to the lower priority one until the CPU is finished with a higher-priority one. The CPU can often "disable interrupts" when it is doing something time-critical. At such times, the only interrupt that can occur is the Non-Maskable Interrupt, which is generally reserved for critical error conditions that have to be dealt with immediately no matter what else is going on.
There are 256 different interrupt vectors in the 8086/8088. Each vector is a far CS:IP address, which is four bytes. That makes the interrupt vector table 1,024 bytes.
In the 8085 microprocessor, a hardware interrupt is a signal from an external device that temporarily halts the CPU's current operations to allow the device to communicate with the processor. A vector interrupt specifically refers to an interrupt that has a predefined memory address (vector) associated with it, which the processor jumps to when servicing the interrupt. For instance, the 8085 has several hardware interrupts, such as INTR, RST 7.5, RST 6.5, and RST 5.5, each with its own unique vector address, allowing for efficient and organized handling of multiple interrupt sources. This mechanism enables real-time processing and responsiveness to external events in embedded systems.
The TRAP interrupt is nomaskable in the 8085 microprocessor because TRAP is intended to indicate some serious system problem, or a hardware assisted debugger single step facility.