How is parallel processing achieved using pipelining?

Answer 1

A very limited form of parallelism is achieved by using pipelining in that several instructions (up to the limit of the depth of the pipeline) are being processed (each at a different stage of instruction processing) at the same time. An example of this using a 6 stage pipeline is as follows:

1. instruction completion (this is the oldest instruction stage)
2. data storage to memory
3. instruction execution & perform input/output
4. data read from memory
5. memory address resolution
6. instruction fetch from memory (this is the newest instruction stage)

This form of parallelism was first used in the IBM 7030 Stretch computer released in 1961 but did not become a common feature in computer architectures until the introduction of RISC in the 1980s.

The main advantage of pipelining is that under normal conditions none of the instruction processing hardware becomes idle. The main disadvantage of pipelining is that unscheduled events (e.g. interrupts, branch mispredictions, arithmetic exceptions) cause pipeline content flushes and having to spend time reloading the now empty pipeline to resume correct processing.

Some computers designed with pipelines having an unusually high number of stages had their performance so degraded by that disadvantage that real world benchmarks showed their performance to be only slightly better than the traditional nonpipelined computers, even though their estimated performance was originally much higher. RISC specified that the number of stages in the pipeline should be kept to a minimum to reduce this problem.