There is insufficient information in the question to properly answer it. You need to specify which FPGA you are interested in. Please restate the question.
yes
The clock out frequency of an 8085 is one half the crystal frequency. The period of one T cycle is the inverse of the clock frequency. At a crystal frequency of 5MHz, the clock is 2.5MHz, and T is 400 ns.
If you have the Maximum clock frequency, then you can figure out the minimum clock period using this formula: 1/(minimum clock period) = (Maximum clock frequency).
How to make Low frequency clock generator using ANAD gates?
that depends on the microcontroller. check the datasheet.
We use clock signal in timing diagram because the microprocessor operates with reference to clock signals provided to it. At pins X1 and X2 we provide clock signals and this frequency is divided by two. This frequency is called as the operating frequency.
Yes, FPGA is used in some ways in mobiles.
The 555 IC timer does not have a clock.
FPGA is sutiable for complicated arch than CPLD. CPLD is very tiny when compared to the logic of FPGA so CPLD is faster.
micro controller is software and fpga is hardware
fpga has fine grain architecture and it can be programmed easily at field
fpga has fine grain architecture and it can be programmed easily at field