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How can you give the input values in vhdl code itself instead of giving the input values in test bench for synthesis in xilinx and where you have to give the input values in vhdl code?
Wiki User
∙ 11y ago
In the "architecture" of VHDL, after "begin" statement,
if you want, you can apply the inputs.
For example,
a<='0';
b<='1'; etc.
But, if you want the inputs to change periodically, then you should at least apply one "enable" or "clock" pulse.
Wiki User
∙ 11y ago
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