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Is it true MRAM chips must be re-energized constantly or they lose their contents?
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What is MRAM?
its a dairymilk....contains delicious flavors.....khani ghar ghar ki....:):)
What is MRAM Magnetoresistive Random Access Memory made of?
Magnetoresistive Random Access Memory
How old MRAM technology is?
1990's. Source: http://en.wikipedia.org/wiki/Magnetoresistive_Random_Access_Memory
How do you solve a math sequence using TI-84 Plus Calculator?
mram ti 84 sequences
When were the Ancient Athens Olympics held?
MRod luv JM MJ luv Andre nd MRam luv KM
Can ps2 emulator run on 512 mram and 128 mb graphic card?
NO.for a ps2 emulater you need at least 2gb ram, and a Pentium 4.
What memory chip retains its data when its power supply is switched off?
Only the various types of ROM: masked ROM, programmable ROM, UVPROM, EEPROM, NOVRAM (which is a SRAM and a EEPROM backup memory on one chip that automatically programs the contents of the entire SRAM in one programming cycle to the EEPROM when power is switching off and then automatically reloads the SRAM with the contents of the EEPROM the moment power is switched on and stable), Flash memory (which performs large "sector" programming cycles instead of individual byte programming cycles, allowing it to act as a solid state disk drive), etc. retain data without power. There has been work on magnetic RAM chips (MRAM) that like the old magnetic core memory stacks will retain memory without power, but they have never been able to be produced at a cost comparable to modern DRAM.
What type of memory can hold data for long periods of time even when the computer is off?
Nonvolatile memory.For small amounts of memory a nonvolatile memory can be created by using conventional semiconductor CMOS static RAM ICs with battery backup (this is used in the CMOS memory on Windows computers and the PRAM on MacOs computers).For medium amounts of memory semiconductor NOVRAM ICs can be used, but they contains both SRAM and EEPROM in the same IC package and requires a "warning signal" from the power supply to copy the contents before power actually fails.For large amounts of memory magnetic memories are about the only way (e.g. ferrite magnetic core, Spin-Torque MRAM ICs, magnetic tunnel junction MRAM ICs).ROM and Flash memory are nonvolatile, but are too slow on writes for practical use.
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What is semiconducter memories?
Definition: A device for storing digital information that is fabricated by using integrated circuit technology. Also known as integrated-circuit memory; large-scale integrated memory; memory chip; semiconductor storage; transistor memory. Semiconductor memory is an electronic data storage device, often used as computer memory, implemented on a semiconductor-based integrated circuit. Examples of semiconductor memory include non-volatile memory such as Read-only memory (ROM), magnetoresistive random access memory (MRAM), and flash memory. It also includes volatile memory such as static random access memory (SRAM), which relies on several transistors forming a digital flip-flop to store one bit, and dynamic random access memory (DRAM), which uses one capacitor and one transistor to store each bits. Shift registers, processor registers, data buffers and other small digital registers that have no memory address decoding mechanism are not considered as memory. Data is accessed by means of a binary memory address to the memory. If the memory address consists of M bits, the address area consists of two raised by M addresses per chip. Semiconductor memory are manufactured with a certain word length (number of 1-bit cells sharing the same memory address) that power of two, typically M=1, 2, 4 or 8 bit per chip. Consequently, the amount of data stored in each chip is MN2 bits. Possible figures are 1, 2, 4, 8, 16, 32, 64, 128, 256 and 512 bit, kbit, Mbit, Gbit and Tbit, here defined by binary prefixes. By combining several integrated circuits, memory can be arranged for a larger word length and/or address space than what is offered by each chip, often but not necesserily a power of two.
What is the function of a memory cell?
Computer systems typically employ a central processing unit (CPU), a display device, input devices, and memory for data storage. Memory devices are typically provided as internal storage areas in the computer. Memory for data storage generally comes in the form of integrated circuit chips. Memory for a computer system is technically any form of electronic, magnetic or optical storage. It is generally divided up into different categories based in part upon speed and functionality. In general, memory types can be categorized according to the storage state into volatile memory and non-volatile memory according to storage type. The primary difference between volatile memory and non-volatile memory is that a volatile memory needs to be supplied with external power in order to hold and refresh data while a non-volatile memory can maintain data for extended periods of time without any power being supplied to the device. Data intended for high-speed short-term access is typically stored in volatile memory. Data intended for long term future access is typically stored in non-volatile memory. Volatile memory currently has faster access times and higher data transfer rates than non-volatile memory. This makes it an appealing alternative for systems requiring very high-speed access to data typically stored in long term, non-volatile storage devices. Most computer systems utilize both volatile and non-volatile memory in the same system or device. In a typical computer system, data intended for high-speed short-term access, such as on-chip memory for the CPU, and often first and second level off-chip memory, are typically stored in volatile memory devices such as a cache or random access memory (RAM, DRAM, SRAM) which typically have nanosecond to microsecond access times. Data intended for long-term storage or mass storage are typically stored in non-volatile storage devices such as magnetic disks, hard disk drives, zip drives, floppy disk drives, tape drives and optical storage media which typically have access times on the order of milliseconds or seconds. Random access memory (RAM) is the main memory of a computer system used for storing programs and data. RAM provides temporary read/write storage while hard disks offer semi-permanent storage. All programs must be run through RAM before they can be used. The term random derives from the fact that the CPU can retrieve data from any individual location, or address, within RAM. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost. The volatile memory typically comprises random access memory (RAM) and is considered the main memory for the computer system. To facilitate quick access for processing, a typical modern computer has a main memory connected by a memory bus directly to the processor. Random access memory is much faster to read from and write to than the other kinds of storage devices in a computer such as the hard disk, floppy disk, and CD-ROM. In contrast to the relatively slow storage memory, the main memory is generally comprised of fast, expensive volatile random access memory (RAM) with access times generally less than 100 nanoseconds. Volatile random access memory (RAM) devices may be further divided into two categories, including static random access memory (SRAM) and dynamic random access memory (DRAM). Static random access memory (SRAM) consists of flip-flop latches, which each retain one bit of data for as long as power is maintained. In dynamic random access memory (DRAM), each memory cell is made up from one transistor and a capacitor. Random access memory is usually used to designate a data memory having a multiplicity of memory cells, each of which can store a datum and which can be accessed selectively and directly to selectively write in or read out data. Random access memories, such as static random access memories or dynamic random access memories, generally comprise a multiplicity of addresses for writing therein data. Data in the addresses may be accessed, for example, through data latches for performing operations, e.g., programming, on a memory cell array, e.g., a non-volatile memory cell array. As a computer system may be used in a variety of ways the amount of RAM deemed appropriate in one instance may be insufficient or superfluous in another. For example, an image processing and manipulation application may not only be time consuming to initialize for use, but also may require the majority of available main memory RAM resources, while a simple text editor may hardly be noticeable to the system. Static random access memory (SRAM) devices have been employed for decades to store electronic data. An SRAM device includes an array of memory cells organized into rows and columns of memory cells. An SRAM cell includes a pair of inverters with the outputs of the inverters cross-coupled to form a flip-flop. The typical SRAM cell includes four transistors for storing data and two transistors for selection of a particular cell. An addressable word line is coupled to the memory cells in a distinct row of memory cells. The memory cells of an SRAM typically have first and second inverters whose inputs and outputs are connected to each other, and first and second transfer transistors that connect the output ends of the first and second inverters to a bit line pair. The first and second inverters include a load transistor and a driver transistor. The memory cells in a column of memory cells are coupled to an addressable pair of bit lines. Data is written to and read from a memory cell in the memory cell array by selecting a row of memory cells and accessing memory cells therein that are coupled to selected bit line pairs. Static random access memory cells typically provide memory storage for bits that can be rapidly read from and written to. Unlike dynamic random access memory (DRAM) cells, because of the flip-flop feedback effect, SRAM cells typically enable storage of static data even without refresh operations. The static random access memory is the main stream of the on-chip memories to be mounted on an LSI together with other parts. In spite of this, the SRAM, since it is composed of six transistors, requires a large space for disposing memory cells, encountering a problem of mounting space when it employed to be mounted on an LSI together with other parts. Due to its larger memory cell size, an SRAM is typically more expensive to manufacture than a DRAM. An SRAM typically has a smaller read access time and lower power consumption than a DRAM. Therefore, where fast access to data or low power is needed, SRAMs are often used to store the data. A dynamic random access memory (DRAM) device is a typical volatile memory device constructed from an array of memory cells. Each memory cell comprises an active device and a capacitor. Furthermore, each memory cell is electrically connected to a word line (WL) and a bit line (BL). A dynamic random access memory includes a large number of memory cells, each of which can store at least one bit of data. In typical DRAM, the coupling of memory cells results in a differential voltage appearing on a bit line (or bit line pair). The differential voltage is amplified by a sense amplifier, resulting in amplified data signals on the bit lines. The applied memory address also activates column decoder circuits, which connect a given group of bit lines to input/output circuits. The memory cells are arranged in an array having a number of rows and columns. Memory cells within the same row are commonly coupled to a word line and memory cells within the same column are commonly coupled to a bit line. The memory cells within the array are accessed according to various memory device operations. Such operations include read operations, write operations and refresh operations. DRAM memory cell stores data by placing charge on, or removing charge from, a storage capacitor. According to the type of capacitor used in each memory cell, dynamic random access memory can be further sub-divided into a stack capacitor DRAM and a deep trench capacitor DRAM. Computer systems and other electronic devices containing a microprocessor or similar device typically include system memory, which is generally implemented using dynamic random access memory. The primary advantage of DRAM is that it uses relatively few components to store each bit of data, and is thus relatively inexpensive to provide relatively high capacity system memory. A disadvantage of DRAM is that their memory cells must be periodically refreshed. Pseudo static random access memory (PSRAM) is another type of DRAM. PSRAM is a low power DRAM having a static random access memory interface for wireless applications. DRAM uses a main clock signal and a data strobe signal (DQS) for addressing the array of memory cells and for executing commands within the memory. The clock signal is used as a reference for the timing of commands such as read and writes operations, including address and control signals. The DQS signal is used as a reference to latch input data into the memory and output data into an external device. Dynamic random access memory uses an interface with address lines that are typically multiplexed in time. DRAM memory devices generally employ a row decoder circuit comprising a decoding unit and a wordline driver to drive a voltage level of a wordline high or low in order to "open" or "close" access to an associated row of memory cells. Such circuits operate to drive the wordline voltage level between a range of a positive voltage, which is greater than a maximum available power supply voltage and a negative voltage, which is less than a reference voltage, such as a ground reference. A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. A synchronous DRAM can perform various functions in synchronism with a clock signal that is supplied from an external source. The synchronous DRAM can refresh itself independently of the computer system which incorporates the synchronous DRAM, by generating refresh addresses inside of the memory using internal addresses. While the synchronous DRAM is being refreshed, word lines are selected to satisfy a refresh period required by the refresh characteristics of cells and a refresh rate required by the computer system. When the synchronous DRAM is in normal operation, a common output word line is provided for a plurality of banks in an interleaved configuration, and only one of the banks is selected at a time. The SDRAM has internal logic used to advance the data address. In addition to the timing signals, certain control registers of the internal logic of the SDRAM must be loaded with timing control parameters before the sequential access mode may be used. Recent advances in memory technology have included the development of magnetic RAM (MRAM). The MRAM is a memory device for reading and writing information wherein multi-layer ferromagnetic thin films is used by sensing current variations according to a magnetization direction of the respective thin films. MRAM uses a ferromagnetic material as one of the next generation memory devices. The MRAM embodies a memory device by using a giant magneto resistive (GMR) or spin-polarized magneto-transmission (SPMT) phenomenon generated when the spin influences electron transmission. MRAM stores information magnetically, so it does not require a constant power supply. This quality is known as non-volatility. A magnetic random access memory (MRAM) element typically has a structure that includes first and second magnetic layers which are separated by a non-magnetic layer. A magnetic vector in one of the two magnetic layers is magnetically fixed or pinned, while the magnetic vector of the other of the two magnetic layers is not fixed and thus its magnetization direction is free to be controlled and switched. Information is written to and read from the element as a logic "1" or a logic "0" by changing the direction of the non-fixed magnetization vector in the other of the two magnetic layers. The differences in magnetization vector direction cause resistance variations within the element which can be measured. MRAM can offer all the advantages in speed and size that volatile memory offers and brings the added advantage of being non-volatile and, in some architectural configurations, cheaper to manufacture. MRAM can operate at speeds similar to either SRAM or DRAM, thus allowing it to be utilized within main memory. The MRAM has a high speed and low power consumption, and allows high integration density due to its unique properties of the magnetic thin film, and also performs a nonvolatile memory operation such as a flash memory. A cache memory and a main memory are used for a large scale integration circuit having a central processing unit. Memory caching is a widespread technique used to improve data access speed in computers and other digital systems. The speed at which processors can execute instructions has typically outpaced the speed at which memory systems can supply the instructions and data to the processors. Due to this discrepancy in the operating speeds of the processors and system memory, the system memory architecture plays a major role in determining the actual performance of the system. Most current memory hierarchies utilize cache memory in an attempt to minimize memory access latencies. A cache is a small, fast memory that acts as a buffer between a device that uses a large amount of memory and a large, slower main memory. The cache's purpose is to reduce average memory-access time. Caches are effective because of two properties of software programs: spatial and temporal locality. Cache memory is used to provide faster access to frequently used instructions and data, which helps improve the overall performance of the system. Caching relies on a property of memory access known as temporal locality. Temporal locality states that information recently accessed from memory is likely to be accessed again soon. Information in cache RAM may be stored based upon two principles, namely spatial locality and temporal locality. The principle of spatial locality is based upon the fact that when data is accessed at an address, there is an above average likelihood that the data which is next required will have an address close to that of the data which has just been accessed. By contrast, temporal locality is based upon the fact that there is an above average probability that data which has just been accessed will be accessed again shortly. Cache memory is typically implemented using static random access memory (SRAM) because such memory need not be refreshed and is thus always accessible for a write or a read memory access. Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Read only memory (ROM) is a non-volatile memory commonly used in electronic equipment such as microprocessor-based digital electronic equipment and portable electronic devices. Read only memory is a type of non-volatile data storage device that can retain stored data even when the power is cut off. Among the memory products, non-volatile memory is one type of memory device having the capacity for writing data into, reading data from and erasing stored data multiples of times. Moreover, data will be retained even if the power to the device is cut off. With these advantages, it has become one of the most widely adopted memory devices in personal computer and electronic equipment. Most standard electrical products are equipped with some read only memory for holding a normal operation. ROM devices typically include multiple memory cell arrays. Each memory cell array may be visualized as including intersecting word lines and bit lines. Each word and bit line intersection can correspond to one bit of memory. In mask programmable metal oxide semiconductor (MOS) ROM devices, the presence or absence of a MOS transistor at word and bit line intersections distinguishes between a stored logic `0` and logic `1`. A ROM array of memory cells is defined by a number of transistors generally arranged in a grid pattern having a plurality of rows and columns. Each individual transistor of each memory cell of the ROM array is placed between a column of the series of columns and a voltage bus. The column is supplied with power at a first predetermined voltage level, and the voltage bus is supplied with power at a second, different predetermined voltage level. A gate of each transistor of a ROM array is connected to a particular row of the series of rows. ROM memories may be included in any type of integrated circuit (IC). In general, ROM memory is used to hold and make available data or code that will not be altered after IC manufacture. Data or code is programmed into ROM memory during fabrication. According to data storage format, read only memory (ROM) can be further sub-divided into mask ROM, one-time programmable ROM (OTPROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) and so on. The one-time electrically programmable read only memory (OTEPROM) permits the writing of data into the memory after leaving the factory. The data can be written by the user to fit a particular memory environment, which is more convenient to a user. Since data can be programmed into a one-time programmable ROM outside the factory according to the particular environment the memory is supposed to be working in, one-time programmable ROM is more convenient to work with than the mask ROM. A mask read only memory (Mask ROM) is a semiconductor memory device in which data required is coded during a manufacturing process. There are two types of Mask ROMs: an embedded diffusion-programmable ROM and an embedded metal programmable ROM. Mask ROM is able to write quaternary data into each memory cell transistor. A large amount of information can be stored in small circuits using this mask ROM. A programmable read only memory (PROM) is similar to the mask programmable ROM except that a user may store data values using a PROM programmer. A PROM device is typically manufactured with fusible links at all word and bit line intersections. An erasable programmable read only memory (EPROM) is programmable like a PROM, but can also be erased by exposing it to ultraviolet light. An EPROM integrated circuit is normally housed in a package having a quartz lid, and the EPROM is erased by exposing the EPROM integrated circuit to ultraviolet light passed through the quartz lid. Most PROMs can only be programmed once, typically by blowing open an appropriate word-to-bit connection path. Conversely, EPROMs can be programmed and reprogrammed multiple times. EPROMs are programmed by injecting hot electrons into, for example, a floating gate dielectrically spaced above the transistor channel. The injected electrons can thereafter be removed by irradiating the floating gate with ultraviolet light. Electrically erasable programmable read-only memory (EEPROM) is a non-volatile memory device that allows multiple data writing, reading, and erasing operations. The structure of EEPROMs is similar to that of erasable programmable read-only memories (EPROMS) since both of them have a floating gate for storing charges and a control gate for controlling data access. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. The electrical charge modifies the electrical characteristics of the EEPROM cell so that the information can be later read back using the modified electrical characteristics. The electrical charge is typically blocked in a trapping layer that gives to the EEPROM cell its memory capability. A typical EPROM device has a floating gate MOS transistor at all word and bit line intersections. Each MOS transistor has two gates: a floating gate and a non-floating gate. The floating gate is not electrically connected to any conductor, and is surrounded by a high impedance insulating material. The floating gates in the EEPROM device are surrounded by a much thinner insulating layer, and accumulated negative charges on the floating gates can be dissipated by applying a voltage having a polarity opposite that of the programming voltage to the non-floating gates. To program the EPROM device, a high voltage is applied to the non-floating gate at each bit location where a logic value is to be stored. This causes a breakdown in the insulating material and allows a negative charge to accumulate on the floating gate. When the high voltage is removed, the negative charge remains on the floating gate. An electrically erasable programmable read-only memory allows multiple data writing, reading and erasing operations. In addition, the stored data will be retained even after power to the device is removed. The EEPROM is very suitable to be used in an embedded function, such as an address book in cell phones, because of its byte program/erase feature. In addition, EEPROM products usually have good high reliability performance, which increases applicability in application fields requiring repetitive programming, reading, and erasing. With these advantages, it has been broadly applied in personal computer and other electronic equipment. A flash memory is a type of flash EEPROM device that can be erased and reprogrammed in blocks instead of one byte at a time. Flash memory devices are different from EEPROM devices in that electrical erasure involves large sections of, or the entire contents of, a flash memory device. A flash memory cell includes a field effect transistor (FET) having a selection gate, a floating gate, a source and a drain. Data is stored in the flash memory cell by variations in the amount of charge stored in the floating gate, which causes a variation in a threshold voltage (Vt) of the flash memory cell. The data stored in the flash memory cell is read out by applying a selection voltage to a word line connected to the selection gate. The flash memory electrically deletes the data using a same method as that of an electrically erasable and programmable ROM (EEPROM), and the memory may be entirely deleted in one second or several seconds. The data stored in the flash memory is deleted throughout the chip in a block unit, but it is impossible to delete the data in a byte unit. The flash memory stores a correctable control program, which is used instead of an auxiliary memory. The flash memory is divided into a NAND flash memory and a NOR type flash memory. The NOR type flash memory uses an interface method as an SRAM or a ROM to easily construct a circuit with a processor. The NOR flash memory employs memory cell arrays that suppress the parasitic resistance. The NOR flash memory lowers the resistance by providing one through-hole to bit line for two cells connected in parallel. A NAND flash memory device is comprised of memory cells serially connected between a drain selection transistor and a source selection transistor in the unit of 16 or 32 in number. The flash memory cells of the NAND flash memory device include a current path formed between the source and drain on a semiconductor substrate, and a floating gate and a control gate that are connected over the semiconductor substrate with an insulator intervened between them. NAND flash memory devices are typically used as mass data storage devices, and NOR flash memory devices are typically used as information storage devices for high speed data processing. Flash memory devices have achieved a commercial success in an electronic industry because they are able to store data for a relatively long time even without a power supply. Flash memory devices are applicable for multiple operations of data writing, reading and erasing, and have the advantage that stored data will not been vanished even after power supply is cut off. Thus, flash memory devices are widely used as non-volatile memory devices for personal computers and other electronic products. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include portable computers, personal digital assistants (PDA), digital cameras, and cellular phones. Program code, system data such as a basic input/output system (BIOS), and other firmware can typically be stored in flash memory devices. Most electronic devices are designed with a single flash memory device. Flash memory devices are finding increasing applications in smart cards for recording, storing and transporting digital information. Flash memory cards are currently used in digital cameras for recording and storing pictures that can be later displayed on personal computers, TVs or printed. Flash memories in smart cards are being used not only for storing data but also for storing application programs such as fingerprint identification, identification cards, health records, transportation programs and many more applications which include encryption for personal security, and also applications such as e-passport, credit card, JAVA card subscriber identity module (SIM).
What about Modern trend in semiconductor memory?
Today's memory and storage hierarchy consists of embedded SRAM on the processor die and DRAM as main memory on one side, and HDDs for high-capacity storage on the other side. Flash memory, in the form of solidstate- disks (SSD), has recently gained a place in between DRAM and HDD, bridging the large gap in latency (105 times) and cost (100 times) between them. However, the use of Flash in applications with intense data traffic, i.e., as main memory or cache, is still hampered by the large performance gap in terms of latency between DRAM and Flash (still 1000 times), and the low endurance of Flash (104 - 105 cycles), which deteriorates with scaling and more aggressive MLC functionality. MLC technology has become the focus of the Flash vendors because they target the huge consumer-electronics market, where the low cost per gigabyte of MLC plays a very important role, but it suffers from endurance and latency issues, which could be problematic for enterprise-class applications. For example, at the 32-nm technology node and 2 bits per cell, it is expected that the standard consumer-grade MLC will offer a write/erase endurance of approx. 3,000 cycles, which clearly will not suffice for enterprise-class storage applications. On the other hand, an enterprise-grade MLC with higher cost per gigabyte could offer a write/erase endurance of 104 to 3 104, albeit with a slower programming latency of approx. 1.6 ms. These limitations of the MLC technology necessitate the use of more complex error-correction coding (ECC) schemes and Flash management functions, which, depending on the workload, could improve the reliability and hide the latency issues to a certain extent- but certainly not to full satisfaction. Moreover, as we go down on the technology node, these issues will be further aggravated, and new challenges will have to be resolved. For example, the stringent data-retention requirements, in particular for enterprisestorage systems, impose a practical limit for the thickness of the tunnel oxide. Another challenge in the scaling of floating-gate NAND is floating-gate interference. To resolve this issue, a charge-trapping layer has been proposed as an alternative technology to the floating gate [2]. In general, it was believed for a long time that by moving to charge-trapping storage it would be possible to scale at least to the 22-nm lithography generation. However, recently a very promising trend towards stacking memory cells in three dimensions in what is called 3D memory technology has emerged, and leading NAND Flash memory manufacturers are already pursuing it [11]. Of course, this 3D memory technology will not truly have an impact on reliability, endurance and latency, but it will offer much larger capacities at even lower cost in the future. For all these reasons, NAND Flash is not 5 expected to become an SCM technology in general. Scaling issues are also critical for other solid-state memories, such as SRAM and DRAM. Specifically, SRAM suffers from signal-to-noise-ratio degradation and 10x leakage increase with every technology node, and DRAM faces a continuous increase of the refresh current. Hence, there is a large opportunity for new solid-state nonvolatile memory technologies with "universal memory" characteristics. These technologies should not only extend the lifetime of existing memories, but also revolutionize the entire memory-storage hierarchy by bridging the gap between memory (fast, expensive, volatile) and storage (slow, inexpensive, permanent). The requirements of this new family of technologies called SCM [1] are nonvolatility, solid-state implementation (no moving parts), low write/read latency (tens to hundreds of nanoseconds), high endurance (more than 108 cycles), low cost per bit (i.e., between the cost per bit of DRAM and Flash), and scalability to future technology nodes. Many new nonvolatile solid-state memory technologies have recently emerged. The objective has not only been to realize dense memory arrays and show a viable scalability roadmap, but also to achieve a performance superior to that of Flash memory in many aspects. The catalog of new technologies is very long, and they may be broadly categorized into charge-trap-based, capacitance-based and resistance-based memories. Charge-trap based memories are basically extensions of the current floating-gate-based Flash and, while offering advantages in reliability, suffer from the same drawbacks that afflict Flash technology, namely, low endurance and slow writing speeds. Capacitance-based memories, in particular ferroelectric memories (FeRAM), exhibit practically infinite cycling endurance and very fast read/write speeds, but are hampered by short retention times and, even more importantly, their limited scaling potential up to the 22-nm node [12]. Resistance-based memories encompass a very broad range of materials, switching mechanisms and associated devices. Following the International Technology Roadmap for Semiconductors (ITRS), one may categorize resistance-based memories into nanomechanical, spin torque transfer, nanothermal, nanoionic, electronic effects, macromolecular and molecular memories [12]. Of these technologies, those that have received more attention by the scientific community and the semiconductor industry and are thus in a more advanced state of research and/or development, are spin torque transfer, nanoionic and thermal memories. We will take a closer look at these technologies next. Spin-torque transfer memory (STTRAM) [13]-[15] is an advanced version of the magnetic random access memory (MRAM) in which the switching mechanism is based on the magnetization change of a ferromagnetic layer induced by a spin-polarized current flowing through it. The most appealing features of STTRAM are its very high read/write speed, on the order of 10 ns or less, and its practically unlimited endurance. Important challenges are overcoming the small resistance range (between low and high resistance), which limits the possibility of MLC storage, and achieving adequate margins not only between read and write voltages but also between write and breakdown voltages for reliable operation, especially at high speeds. Nanoionic memories [16]-[21] are characterized by a metal-insulator-metal (MIM) structure, in which the "metal" typically is a good electrical conductor (possibly even dissimilar on the two sides of the device) and the "insulator" consists of an ion-conducting material. Typical insulator materials reported so far include binary or ternary oxides, chalcogenides, metal sulfides, and even organic compounds. The basic switching mechanism in nanoionic memories is believed to be the combination of ionic transport and electrochemical redox reactions [19]. Most of these technologies-with very few exceptions-are still in a very early stage of research, with many of their interesting features derived from projections or extrapolations from limited experimental data. As is generally known, the actual issues associated with a particular technology will likely only manifest themselves in large demonstration device test vehicles, so that it may well be that the road to widespread adoption of nanoionic memories is still a long one. The best known thermal memory is phase-change memory (PCM). This discussion focuses on PCM, mainly because of the very large activity around it and the advanced state of development it has reached, allowing credible projections regarding its ultimate potential. The active material in PCM is a chalcogenide, typically involving at least two of the materials Ge, Sb and Te, with the most common compound being Ge2Sb2Te5 6 or, simply, GST. The active material is placed between two electrically conducting electrodes. The resistance switching is induced by the current flowing through the active material, which causes a structural change of the material due to Joule heating. Phase-change materials exhibit two meta-stable states, namely, a (poly)- crystalline phase of long-range order and high electrical conductivity and an amorphous phase of short-range order and low electrical conductivity. Switching to the amorphous phase (the RESET transition) is accomplished by heating the material above its melting temperature followed by ultra-fast quenching, whereas the crystalline phase (SET transition) is reached by heating the materials above its crystallization temperature and subsequent annealing. The RESET transition necessitates high current, but this current has been shown to scale linearly with the technology node as well as decrease significantly in confined memory cell architectures . The RESET transition is fast, typically less than 50 ns in duration, whereas the SET transition is on the order of 100 ns, although very fast materials exhibiting sub-20-ns switching times have been reported . PCM scores well in terms of most of the desirable attributes of a SCM technology. In particular, it exhibits very good endurance, typically exceeding 108 cycles, excellent retention, and superb scalability to sub-20-nm nodes and beyond. Most importantly, these characteristic numbers have been measured on large prototype devices and thus provide confidence regarding the true performance of the memory technology. On a smallerscale device level, PCM has been shown to possess all the necessary characteristics of a SCM technology. Specifically, sub-20-ns SET switching times have been reported with doped SbTe materials [23]. Furthermore, an impressive device has been fabricated at the 17-nm design rule at 4F2 size, with further scaling prospects not limited by lithography but only by the material film thickness . The same device showed an extrapolated cycling endurance exceeding 1015 cycles. The ultimate scaling limits of phase change in chalcogenide materials provide an indication regarding the future scaling of PCM. In a recent study, GST films that are a mere 2 nm thick have been shown to crystallize when surrounded by proper cladding layers . Apart from the necessary RESET current reduction and SET speed improvement discussed above, a significant challenge of PCM technology is a phenomenon known as (short-term) resistance drift: The resistance of a cell is observed to drift upwards in time, with the amorphous and partially-amorphous states drifting more than their crystalline counterparts. This drift is believed to be of electronic nature, manifests itself as noise, and seriously affects the reliability of MLC storage in PCM because of the reduced sensing margin between adjacent tightly-packed resistance levels. Therefore, effective solutions of the drift issue are a key factor of the cost competitiveness of PCM technology and thus of its suitability as SCM. In summary, PCM is the only one of numerous emerging memory technologies that has evolved from the basic research stage to the advanced development and late prototyping stage without encountering any fundamental roadblocks. Advanced prototype PCM chips that at least partially meet the requirements for SCM already exist today, and new and exciting device demonstrations have shown tremendous potential for further improvement. These developments render PCM the leading technology candidate for SCM today, with the potential to play an extended role in the memory and storage hierarchy of future computing systems.
