Timing diagram of 8085 microprocessors

Answer 1

A minimum mode of 8086 configuration depicts a stand alone system of computer where no other processor is connected. This is similar to 8085 block diagram with the following difference. The Data transceiver block which helps the signals traveling a longer distance to get boosted up. Two control signals data transmit/ receive are connected to the direction input of transceiver (Transmitter/Receiver) and DEN* signal works as enable for this block. This is the same as Read cycle Timing Diagram except that the DT/R* line goes high indicating it is a Data Transmission operation for the processor to memory / peripheral. Again DEN* line goes low to validate data and WR* line goes low, indicating a Write operation In the maximum mode of operation of 8086, wherein either a numeric coprocessor of the type 8087 or another processor is interfaced with 8086. The Memory, Address Bus, Data Buses are shared resources between the two processors. The control signals for Maximum mode of operation are generated by the Bus Controller chip 8788. The three status outputs S0*, S1*, S2* from the processor are input to 8788. The outputs of the bus controller are the Control Signals, namely DEN, DT/R*, IORC*, IOWTC*, MWTC*, MRDC*, ALE etc. These control signals perform the same task as the minimum mode operation. However the DEN is an active HIGH signal which has to be converted to active LOW by means of an inverter.

Answer 2

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