What is VHDL program for 8 to 1 multiplexer?

Answer 1

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux8X1 is

Port ( en8 : in STD_LOGIC;

s3 : in STD_LOGIC_VECTOR (2 downto 0);

i : in STD_LOGIC_VECTOR (7 downto 0);

y8 : out STD_LOGIC;

y8l : out STD_LOGIC);

end mux8X1;

architecture Behavioral of mux8X1 is

begin

process(en8,s3,i)

begin

if(en8='0') then y8<='0';y8l<='1';

else

case s3 is

when "000" =>y8<=i(0);y8l<=not i(0);

when "001" =>y8<=i(1);y8l<=not i(1);

when "010" =>y8<=i(2);y8l<=not i(2);

when "011" =>y8<=i(3);y8l<=not i(3);

when "100" =>y8<=i(4);y8l<=not i(4);

when "101" =>y8<=i(5);y8l<=not i(5);

when "110" =>y8<=i(6);y8l<=not i(6);

when "111" =>y8<='i(7);y8l<=not i(7);

when others=>' null';

end case;

end if;

end process;

end Behavioral;

Answer 2

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux16x1 is
Port ( d : in STD_LOGIC_VECTOR (15 downto 0);
en : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC;
yn : out STD_LOGIC);
end mux16x1;

architecture structural of mux16x1 is

signal c:std_logic_vector(3 downto 0);
signal ybar:STD_LOGIC_VECTOR (3 downto 0);


component mux4X1
Port ( en4 : in STD_LOGIC;
i3 : in STD_LOGIC;
i2 : in STD_LOGIC;
i1 : in STD_LOGIC;
i0 : in STD_LOGIC;
s2 : in STD_LOGIC_VECTOR (1 downto 0);
y4 : out STD_LOGIC;
y4l : out STD_LOGIC);
end component;

begin

u0:mux4x1 port map (en,d(15),d(14),d(13),d(12),s(1 downto 0),c(3),ybar(3));
u1:mux4x1 port map (en,d(11),d(10),d(9),d(8),s(1 downto 0),c(2),ybar(2));
u2:mux4x1 port map (en,d(7),d(6),d(5),d(4),s(1 downto 0),c(1),ybar(1));
u3:mux4x1 port map (en,d(3),d(2),d(1),d(0),s(1 downto 0),c(0),ybar(0));
u4:mux4x1 port map (en,c(3),c(2),c(1),c(0),s(3 downto 2),y,yn);

end structural;