What is machine cycle and the steps to draw timing diagram?

Answer 1

A machine cycle is three or more T cycles used to perform a memory / IO read or write, or an interrupt acknowedge

1. Draw a square clock oscillator waveform of at least 3 cycles, more if you want to show READY timing.
2. Each T cycle starts at the falling edge of clock, with the first T cycle starting with ALE.
3. Draw an ALE pulse, one half clock cycle, inverted and slightly delayed from clock.
4. Approximately 1/3 into ALE, draw the IO/M-, S0, S1, and A8-A15 lines becoming valid. They stay valid for the duration of the cycle.
5. Approximately 1/3 into ALE, draw the AD0-AD7 lines becoming valid as A0-A7. Note that external logic must strobe these lines on the falling edge of ALE. The AD0-AD7 lines remain valid for about 1 clock cycle.
6. On the second T cycle, draw the RD-, WR-, or INTA- lines becoming valid. The determination is known in advance if one looks at IO/M-, S0, and S1. They are valid for 1.5 clock cycles, except see READY logic below.
7. Show the READY line being sampled in the rising edge of clock after ALE falls. If READY is false at that point, T2 will be repeated until READY is sampled true.
8. As noted AD0-AD7 float 1/2 clock cycle after ALE. 1/2 clock cycle later, they become D0-D7, and drive for WR- or stay floating for RD- or INTA-.
9. External logic is expected to strobe D0-D7 data at the rising edge of WR-. D0-D7 will remain valid for 1/2 clock beyond WR-.
10. External logic is expected to drive D0-D7 during RD- or INTA-. The processor will strobe D0-D7 1/2 clock cycle before the rising edge of RD- or INTA-.
11. Note: Address to read data valid timing is 2 clock cycles, and address to write data valid timing is 2.5 clock cycles. The difference is due to who controls the AD0-AD7 bus, and when it gets strobed.
12. 1/2 clock cycle after RD-, WR-, or INTA-, at the rising edge of clock, the machine cycle ends. Depending on whether or not internal processing must be done, ALE may or may not be emitted, starting another machine cycle.
13. HOLD is sampled on the falling edge of clock in the third T cycle. If recognized, HLDA is asserted 1/2 clock cycle later, 1/2 clock cycle later, the whole control bus floats so another bus master can take over.