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If the FAN-IN exceeds FAN-OUT, then the VIH and VIL levels would not be met, and bus operation would be erratic at best and non-functional at worst. If the capacitance load were exceeded, then slow bus transactions might work, while fast bus transactions might fail. All of this would be dependent on the preceeding state of the bus, so "erratic" would be the least of your troubles. Its also possible that, with inadequate buffering, the bus would ring and, on a scope, would appear to work, but, at strobe time, the logic value would be unreliable.

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Q: What would happen if the address data and control buses were not buffered?
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