There is insufficient information in the question to properly answer it. Which Motorola microprocessor are you talking about? Please restate the question.
In the 8086 microprocessor, code segment addresses are generated using a segment:offset addressing scheme. The code segment (CS) register holds the starting address of the code segment, while the instruction pointer (IP) register holds the offset of the next instruction to be executed within that segment. The effective address of an instruction is calculated by adding the value in the CS register (shifted left by 4 bits) to the value in the IP register, allowing for a total addressable space of 1 MB. This segmentation allows for efficient memory management and organization of code.
Physical address in the 8086/8088 is {Selected Segment Register} * 16 + {Effective Offset Address}. It is a 20-bit address .
INC {register} Example: INC A
There are four segment registers in the 8086/8088, Code Segment (CS), Stack Segment (SS), Data Segment (DS), and Extra Segment (ES). As a result, there are four segments that can be directly addressed at a particular time, i.e. without an extra instruction to reload a segment register.
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The code segment register (CS) is a key component in the architecture of x86 microprocessors, such as those developed by Intel. It holds the starting address of the segment that contains executable code, allowing the CPU to access instructions efficiently. The CS register works in conjunction with instruction pointers to enable the execution of programs by defining the memory segment from which the processor fetches instructions. This segmentation helps manage memory, providing a level of organization and protection for code execution.
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DI is the Index register in Data segment(16-bit, 64 KB) .Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions.
The physical address in the 8086/8088 is calculated by adding the effective address with the contents of one of the segment registers left shifted by 4 bit positions. This results in a 20 bit address bus. As an example, if the CS register contains 1234H, and the IP register contains 5678H, then the next instruction is fetched from physical address 179B8H, which is 1234H times 16 (12340H) plus 5678H. The segment register used is selected by context, or by using a segment override prefix, however, the code segment register (CS) can not be overidden during instruction fetch, nor can the stack segment register (SS) be overidden during stack pushes and pops.
Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions. Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions. Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions. Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions.
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The default segment register for the Instruction Pointer (IP) in x86 architecture is the Code Segment (CS) register. This register is used to define the segment of memory that contains the currently executing code. When a program is executed, the CPU uses the CS register in conjunction with the IP register to determine the address of the next instruction to execute.