Interrupt are automatically disabled on interrupt entry (except for TRAP, which is non-maskable) so that interrupts do not, by default, nest. You would also disable enterrupts surrounding a critical section of code that, perhaps, manipulated an interrupt register. It is possible to re-enable interrupts during an interrupt service routine. Typically, you would have a hierarchy, such as RST7.5, then RST 6.5, then RST 5.5. Initially, at interrupt entry, all interrupts are disabled. You could then manipulate the interrupt mask using the RIM and SIM instructions and enable further interrupts, allowing a nested architecture. At interrupt exit, then, you would disable interrupts, reset the mask, enable interrupts, and return from interrupt.
There are 2 types interrupts in 8085 such as: 1)hardware interrupt 2)software interrupt
The pins used to control interrupts in the 8085 are INTR/INTA, RST5.5, RST6.5, RST7.5, and TRAP.
DI = Disable all interrupts (except TRAP) EI = Enable all interrupts Also, SIM can selectively mask RST5.5, RST6.5, and RST7.5.
The 8085 has a single +5V power supplyThe 8085 has a multiplexed low order address busThe 8085 has extra single pin interrupts, TRAP, RST7.5, RST6.5, and RST5.5The 8085 has serial I/O pins SID and SODThe 8085 has maskable interrupts and the RIM/SIM instructionThe 8085 includes the functionality of the 8224 clock genereator and 8228 system controllerThe 8085 added several 16 bit operations
The hardware initiates an interrupt when it feels that the situation requires the CPU's action.
masking of interrupts is the temporal disabling of the current code the processor is executing to let higher priority ISRs (interrupt Services Routine) to be executed.
Interrupts are not sufficient in multiprocessor systems since disabling inter rupts only prevents other processes from executing on the processor in which inter rupts were disabled; there are no limitations on what processes could be executing on other processors and therefore the process disabling interrupts cannot guarantee mutually exclusive access to program state.
The lowest priority interrupt in the 8085 microprocessor is INTR, unless you also consider the software interrupts, RST 0 through RST 7, which are even lower.
Four of the interrupts in the Intel 8085 (INTR, RST5.5, RST6.5, and RST7.5) are maskable, while one interrupt (TRAP) is non-maskable.The eight RSTx type of software "interrupts" are not really interrupts, but if they were treated as interrupts, they would be non-maskable.
At reset, the 8085 starts at location 0000H. The INTR interrupt goes wherever the interrupt opcode says to go. The TRAP interrupt goes to 0024H. The RST5.5, RST6.5, and RST7.5 interrupts go to 002CH, 0034H, and 003CH respectively. The RST X interrupts goto 0000H plus 10H times X, i.e. 0000H, 0008H, 0010H, ..., 0038H.
if u want to execute high priority interrupt,at that time of low priority running.So, we can mask the low priority interrupt and execute the high priority interrupt.
TRAP is a non maskable interrupt pin in 8085.....it has the highest priority out of all the interrupts...it is used in emergency n critical states..ex.during power loss etc.