What are Interrupts and their types?

Answer 1

In computing, an interrupt is an asynchronous signal indicating the need for attention or a synchronous event in software indicating the need for a change in execution.

A hardware interrupt causes the processor to save its state of execution and begin execution of an interrupt handler. Software interrupts are usually implemented as instructions in the instruction set, which cause a context switch to an interrupt handler similar to a hardware interrupt.

Interrupts are a commonly used technique for computer multitasking, especially in real-time computing. Such a system is said to be interrupt-driven.

An act of interrupting is referred to as an interrupt request (IRQ).

Types of Interrupts

1. Level-triggered

A level-triggered interrupt is an interrupt for which an unserviced interrupt is indicated by a particular state, high level or low level, of the interrupt request line. A device wishing to signal an interrupt drives the line to its active level, and then holds it at that level until serviced. It ceases asserting the line when the CPU commands it to or otherwise handles the condition that caused it to signal the interrupt.

2. Edge-triggered

An edge-triggered interrupt is an interrupt signalled by a level transition on the interrupt line, either a falling edge (high to low) or a rising edge (low to high). A device wishing to signal an interrupt drives a pulse onto the line and then releases the line to its inactive state. If the pulse is too short to be detected by polled I/O then special hardware may be required to detect the edge.

Edge-triggered interrupts do not suffer the problems that level-triggered interrupts have with sharing. Service of a low-priority device can be postponed arbitrarily, and interrupts will continue to be received from the high-priority devices that are being serviced. If there is a device that the CPU does not know how to service, it may cause a spurious interrupt, or even periodic spurious interrupts, but it does not interfere with the interrupt signalling of the other devices. However, it is fairly easy for an edge triggered interrupt to be missed - for example if interrupts have to be masked for a period - and unless there is some type of hardware latch that records the event it is impossible to recover. Such problems caused many "lockups" in early computer hardware because the processor did not know it was expected to do something. More modern hardware often has one or more interrupt status registers that latch the interrupt requests; well written edge-driven interrupt software often checks such registers to ensure events are not missed.

3. HybridSome systems use a hybrid of level-triggered and edge-triggered signalling. The hardware not only looks for an edge, but it also verifies that the interrupt signal stays active for a certain period of time.

A common use of a hybrid interrupt is for the NMI (non-maskable interrupt) input. Because NMIs generally signal major -- or even catastrophic -- system events, a good implementation of this signal tries to ensure that the interrupt is valid by verifying that it remains active for a period of time. This 2-step approach helps to eliminate false interrupts from affecting the system.

4. Message-signaled

Main article: Message Signaled Interrupts

A message-signalled interrupt does not use a physical interrupt line. Instead, a device signals its request for service by sending a short message over some communications medium, typically a computer bus. The message might be of a type reserved for interrupts, or it might be of some pre-existing type such as a memory write.

Message-signalled interrupts behave very much like edge-triggered interrupts, in that the interrupt is a momentary signal rather than a continuous condition. Interrupt-handling software treats the two in much the same manner. Typically, multiple pending message-signalled interrupts with the same message (the same virtual interrupt line) are allowed to merge, just as closely spaced edge-triggered interrupts can merge.

5. DoorbellIn a push button analogy applied to computer systems, the term doorbell or doorbell interrupt is often used to describe a mechanism whereby a software system can signal or notify a computer hardware device that there is some work to be done. Typically, the software system will place data in some well known and mutually agreed upon memory location(s), and "ring the doorbell" by writing to a different memory location. This different memory location is often called the doorbell region, and there may even be multiple doorbells serving different purposes in this region. It's this act of writing to the doorbell region of memory that "rings the bell" and notifies the hardware device that the data is ready and waiting. The hardware device would now know that the data is valid and can be acted upon. It would typically write the data to a hard disk drive, or send it over a network, or encrypt it, etc

Answer 2

An interrupt in the 8085 microprocessor is a request to stop program execution and go do something else, such as service a device request or hardware condition. The interrupt return sequence restores normal program flow to where it was interrupted. An interrupt cycle is a memory fetch sequence generated in response to the interrupt request. It can be identified in hardware by the status lines, and the expected response is an op-code, optionally followed by immediate bytes, such as the address of a CALL instruction. Except, see interrupt types below. There are three types of interrupts: The INTR pin causes a (traditional 8080) hardware interrupt cycle, where the external hardware provides an out-of-band opcode. This is usually an RST instruction or a CALL instruction. The RST instructions generate a software interrupt that vectors to low memory. There are eight RST instructions, RST 0 through RST 7. The number is multiplied by 8, and that is the address of the next instruction to execute, 0H, 8H, 10H, etc. The RST5.5, RST6.5, RST7.5, and TRAP pins are hardware interrupts. Unlike the INTR pin, they do not require the hardware to provide an opcode. Instead, they implicitly generate the equivalent of an RST instruction. They are named x.5 because they fit in halfway between the traditional RST vectors, i.e. RST6.5 vectors to 34H, in between 30H for RST 6 and 38H for RST 7. TRAP is at 24H. RST5.5 and RST6.5 are level triggered. They must be cleared before the IE flag is enabled. RST 7.5 is edge triggered, and will not be triggered until the next leading edge. The IE flag must still be re-enabled. TRAP is both edge and level triggered. It sets at leading edge, and must remain asserted until the interrupt sequence starts. It will refire on next edge, and it cannot be disabled. The interrupt service routine is expected to save and restore the machine state, so that the interrupted program is not disturbed. Except for the delay in processing.