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What is the meaning of static in Static timing analysis?

Static is because you dont use vectors here (STA). In STA you just calculate the timings based on the signal transitation times and cell delays. Hence vectors are not applied and propagated through your circuit. Thanks, bits_dude


What are the latest research topics in VLSI?

vlsi is nothing but a methodology to design a chip.tremendous openings are there in vlsi (chip desining) field.We have to relate embedded system,dsp,bio-medical applications,cmos desisinging etc....these are all common things related to vlsi ,especially in desining field RTL desining ,STA (ststic timing analysis) functional verification,power analysis,synthesizer etc...


Is syllabus of vlsi and vlsi design of MTech of RGPV are same?

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