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entity decoder3x8 is

port ( ctrl : in std_logic_vector (2 downto 0);

z : out std_logic_vector (7 downto 0) );

end decoder3x8;

architecture dec3x8_Dflow of decoder3x8 is

begin

z <= "00000001" when ctrl = "000" else

"00000010" when ctrl = "001" else

"00000100" when ctrl = "010" else

"00001000" when ctrl = "011" else

"00010000" when ctrl = "100" else

"00100000" when ctrl = "101" else

"01000000" when ctrl = "110" else

"10000000" ;

end dec3x8_Dflow;

-- the above code is dataflow modelling...still other modelling, ie structural and

--sequential

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