What is the VHDL program for 5 bit shift register?

Answer 1

A 5-bit shift register in VHDL can be implemented using a process that captures the input data and shifts it through a 5-bit vector on each clock cycle. Here is a simple example:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shift_register is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           data_in : in STD_LOGIC;
           data_out : out STD_LOGIC_VECTOR(4 downto 0));
end shift_register;

architecture Behavioral of shift_register is
    signal register : STD_LOGIC_VECTOR(4 downto 0) := (others => '0');
begin
    process(clk, reset)
    begin
        if reset = '1' then
            register <= (others => '0');
        elsif rising_edge(clk) then
            register <= register(3 downto 0) & data_in;
        end if;
    end process;
    data_out <= register;
end Behavioral;

This code defines a 5-bit shift register that shifts in data_in on each rising clock edge and resets when reset is high.