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conclusion fir sr flip flop

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9y ago
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3y ago

At the standard running of SR NAND Flip-Flop, both NAND inputs must normally be logic 1 level. Thus, the logic level of the Q and outputs will become relative.

While both R and S inputs become logic 0 levels in the same period, it is forbidden. In this state, both Q and outputs will become logic 1 level. Hence, that will override the load-back motion. The final state of the latch will not be resolved in front of time.

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Q: Conclusion for R-S flip flop
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