the current in the drain circuit of a field effect transistor.
Remains constant
The gate voltage controls the extent of depletion layer and thereby controls the width of the channel. As the width of the channel varies, current also varies. Width of the channel is inversly proportional to drain current.
Zin=Vds/Id [Vds=drain to source voltage ; Id = drain current]
Gate reverse bias
the current in the drain circuit of a field effect transistor.
Since CMOS can be NAND and NOR logic this question seems to make little sense. However. If you by any chance think about CMOS Design versus TTL Design then this is a most interresting question. CMOS drain little current at low speed. As speed increases, the drain increases. TTL drain much the same current no matter the speed. There have been made TTL families that only use a little current. This will some times make this family preferable to CMOS. Especially true regarding high frequency logic circuitry. The benefit from TTL is that one output can source 8-14 inputs (Depending on family) CMOS is an ideal choice for low frequency battery operated equipment. It does not provide long batterylife at high frequencies though as drain of current increases.
Increase pitch or increade piping diameter
Remains constant
drain resistane is basically the resistance offered by the drain terminal of the fet device.its the ratio of change in drain to source voltage to the change in drain current at a constant gate to source voltage.
JFET BFW20 shows negetive resistance when gate is grounded (VGS = 0) and vary Drain to source voltage and measure Drain current. As the voltage is increased, the drain current decreases. Prof.S.Lakshminarayana.
Drain is the answer
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The gate voltage controls the extent of depletion layer and thereby controls the width of the channel. As the width of the channel varies, current also varies. Width of the channel is inversly proportional to drain current.
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Zin=Vds/Id [Vds=drain to source voltage ; Id = drain current]
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