6 List and briefly define the functional group s for PCI of signal line?

Answer 1

System pins: Include the clock and reset pins. Address and data pins: Include 32 lines that are time multiplexed for addresses and data. Interface control pins: Control the timing of transactions and provide coordination among initiators and targets. Arbitration pins: Unlike the other PCI signal lines, these are not shared lines. Rather, each PCI master has its own pair of arbitration lines that connect it directly to the PCI bus arbiter. Error Reporting pins: Used to report parity and other errors. Interrupt Pins: These are provided for PCI devices that must generate requests for service. Cache support pins: These pins are needed to support a memory on PCI that can be cached in the processor or another device. 64-bit Bus extension pins: Include 32 lines that are time multiplexed for addresses and data and that are combined with the mandatory address/data lines to form a 64-bit address/data bus. JTAG/Boundary Scan Pins: These signal lines support testing procedures defined in IEEE Standard 1149.1.

Answer 2

PCI.These are divided into the following functional groups:

• System pins: Include the clock and reset pins.

• Address and data pins: Include 32 lines that are time multiplexed for addresses

and data. The other lines in this group are used to interpret and validate

the signal lines that carry the addresses and data.

• Interface control pins: Control the timing of transactions and provide coordination

among initiators and targets.

• Arbitration pins: Unlike the other PCI signal lines, these are not shared lines.

Rather, each PCI master has its own pair of arbitration lines that connect it directly

to the PCI bus arbiter.

• Error reporting pins: Used to report parity and other errors.

Answer 3

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