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Library ieee;
use ieee.std_logic_1164.all;
entity v3to8dec is
port (g1, g2, g3: in std_logic; a : in std_logic_vector (2 downto 0);
y : out std_logic_vector (0 to 7) );
end v3to8dec;
architecture v3to8dec_a of v3to8dec is
signal y_s: std_logic_vector (0 to 7);
begin
with a select y_s <=
"10000000" when "000",
"01000000" when "001",
"00100000" when "010",
"00010000" when "011",
"00001000" when "100",
"00000100" when "101",
"00000010" when "110",
"00000001" when "111",
"00000000" when others;
Y <= y_s when (g1 and g2 and g3) = '1' else "00000000";
end v3to8dec_a;
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