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Very Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) is a technology used to fabricate integrated circuits (IC). The various stages of design, simulation, synthesis, timing analysis, layout and fabrication can be discussed in this category. It is a wide spread technology as most of the existing technologies are digital technologies and need an IC to implement. It is VLSI which made computer to be of the size of a pocket from the size of two rooms.
703 Questions
Where can one purchase a CMOS battery?
CMOS batteries can be purchased at a range of online, local departmental stores with electronic departments and hardware stores. It is usually a good idea to research the brand and type of battery required by visiting the local shops and looking online for the best prices to get the best deal.
What is VHDL program for half adder in behavioral model?
PROGRAM:
Library ieee;
use ieee.std_logic_1164.all;
entity ha1 is
port(a,b:in bit;s,c:out bit);
end ha1;
architecture ha1 of ha1 is
begin
s<=a xor b;
c<=a and b;
end ha1;
What is the difference between 64 bit carry select adder and carry select adder?
Carry select adder is used to select the carry during addition of two numbers. If those numbers are of 64 bits, then we call it as a 64 bit carry select adder.
Where and how do you declare buried nodes in VHDL?
In VHDL, buried nodes, also known as "implicit signals," are typically declared within the architecture of a design entity. You can declare them as signals in the architecture section using the signal keyword. These nodes are not visible outside the architecture and are used for internal connections between components or processes. For example, you might declare a buried node like this: signal buried_signal : std_logic;.
Can you turn a diode in the wrong direction?
Yes, a diode can be connected in the wrong direction, which is known as reverse biasing. In this configuration, the diode will not conduct current under normal operating conditions, effectively acting as an open circuit. However, if the reverse voltage exceeds the diode's breakdown voltage, it may conduct in reverse, potentially damaging the diode. Therefore, it's important to connect diodes with the correct polarity to ensure proper functionality.
What are applications of peak detector?
Amplitude measurementAutomatic gain control
Data regeneration
What is the difference between positive and negative masks?
Masks are used to clear the material of a semiconductor. It is done by exposing the silicon wafer to UV rays and then washing it in a solvent.
- A positive photo mask is used to remove the film wherever the mask is clear
- A negative photo mask is used to remove the opaque
- A positive photo mask requires longer exposure than that of the negative
What is annealing in IC fabrication?
Annealing is the heat treatment given to a semiconductor material. Annealing is the process by which the lattice damages are repaired. The damages are generally done by ion implantation on semiconductor material.
What are the various lithography techniques?
The various lithography techniques are
- Photolithography
- X-ray lithography
- e-beam lithography
- Ion beam lithography
What is meant by metallization in IC fabrication?
Metallization is a technique used to form metal contacts and interconnects in the fabrication of ICs.
What is lithography in IC fabrication?
Lithography is a technique used to make patterns on semiconductor materials.
What is the use of pseudo nMOS gates in digital design?
These circuits use nMOS for implementation of a whole gate + one pMOS which is connected between positive supply and nMOS.
Can transistors have four legs?
In case of a bipolar junction transistor, we have only three terminals (legs). They are emitter, base and collector.
But, in case of a MOSFET (metal oxide semiconductor field effect transistor), we can have four legs. They are source, drain, gate and substrate. The substrate is not being shown in some notations of MOSFET. But it does exist. Hence, a MOSFET has four legs.
What is the functions of cmos to the motherboard?
CMOS (complementary metal oxide semi conductor) is a logic family. A logic family refers to the way of implementing logic. Using this technique, logic gates are realized. The combination of several logic gates forms a digital circuit or integrated circuit (IC). A mother board is also an IC. The technique used to realize it is CMOS logic.
On which day we celebrate engineers day?
September 15 is celebrated every year in India as Engineer's Day to commemorate the birthday of the legendary engineer Sir M. Visvesvaraya
TTL is a logic family. A logic family is the set of logic gates designed using a specific approach. Or simply speaking, logic family is the way of implementing logic. TTL stands for transistor - transistor - logic. It involves transistors (BJT) to implement logic. TTL applies means TTL logic family is used or can be applied in that specific application.
What is VHDL program for half adder in structural model?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity has is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end has;
architecture structural of has is
-- component declaration
component xorg
Port ( p : in STD_LOGIC;
q : in STD_LOGIC;
r : out STD_LOGIC);
end component;
component andg
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end component;
begin
u0:xorg port map (a,b,s);
u1:andg port map (a,b,c);
end structural;
What is VHDL program for full adder in data flow model?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadf is
Port ( ain : in STD_LOGIC;
bin : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end fadf;
architecture df of fadf is
begin
sum<= ain xor bin xor cin;
cout<= (ain and bin) or ( bin and cin) or (ain and cin);
end df;
What is VHDL program for full adder in behavioral model?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fabehv is
Port ( ain : in STD_LOGIC;
bin : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end fabehv;
architecture Behavioral of fabehv is
signal s:std_logic_vector(2 downto 0);
begin
process(ain,bin,cin,s)
begin
s(2)<= ain; s(1)<= bin; s(0)<= cin;
case s is
when "000" => sum<='0'; cout<='0';
when "001" => sum<='1'; cout<='0';
when "010" => sum<='1'; cout<='0';
when "011" => sum<='0'; cout<='1';
when "100" => sum<='1'; cout<='0';
when "101" => sum<='0'; cout<='1';
when "110" => sum<='0'; cout<='1';
when "111" => sum<='1'; cout<='1';
when others => null;
end case;
end process;
end Behavioral;
What is VHDL program for full adder in structural model?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fa is
Port ( ain : in STD_LOGIC;
bin : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end fa;
architecture struct of fa is
-- signal declaration
signal s1,s2,s3:std_logic;
--component declaration
component had
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end component;
component org
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end component;
begin
-- component instantiation or mapping
u1:had port map (ain,bin,s1,s2);
u2:had port map (s1,cin,sum,s3);
u3:org port map (s2,s3,cout);
end struct;
What is VHDL program for serial adder in behavioral model?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SA_VHDL is
Port ( I : in std_logic_vector(15 downto 0);
O : out std_logic_vector(7 downto 0);
c_i, a_i, b_i, c_o, s_o : out std_logic;
CLK : in std_logic;
Load : in std_logic);
end SA_VHDL;
architecture Behavioral of SA_VHDL is
signal ina, inb, oreg : std_logic_vector(7 downto 0);
signal so, ci, co: std_logic;
begin
--reg ina
process (CLK)
begin
if CLK'event and CLK='1' then
if (Load='1') then
ina <= I(15 downto 8);
else
ina <= '0' & ina(7 downto 1);
end if;
end if;
end process;
--reg inb
process (CLK)
begin
if CLK'event and CLK='1' then
if (Load='1') then
inb <= I(7 downto 0);
else
inb <= '0' & inb(7 downto 1);
end if;
end if;
end process;
--oreg
process (CLK)
begin
if CLK'event and CLK='1' then
if (Load='1') then
oreg <= "00000000";
ci <= '0';
else
ci <= co;
oreg <= so & oreg(7 downto 1);
end if;
end if;
end process;
-- FA
so <= inb(0) xor ina(0) xor ci;
co <= (inb(0) and ina(0)) or
(inb(0) and ci) or
(ci and ina(0));
O <= oreg;
-- for test
c_i <= ci;
a_i <= ina(0);
b_i <= inb(0);
c_o <= co;
s_o <= so;
end Behavioral;
What is VHDL program for parallel adder?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pa is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
ci : in STD_LOGIC;
co : out STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0));
end pa;
architecture Behavioral of pa is
--signal declaration
signal c:std_logic_vector(2 downto 0);
--component declaration
component fadf
Port ( ain : in STD_LOGIC;
bin : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end component;
begin
u0:fadf port map(a(0),b(0),ci,s(0),c(0));
u1:fadf port map(a(1),b(1),c(0),s(1),c(1));
u2:fadf port map(a(2),b(2),c(1),s(2),c(2));
u3:fadf port map(a(3),b(3),c(2),s(3),co);
end Behavioral;
What is VHDL program for carry look ahead adder?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cldf IS
PORT
( a : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ci : IN STD_LOGIC;
sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
co : OUT STD_LOGI );
END cldf;
ARCHITECTURE df OF cldf IS
SIGNAL h_sum : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL g : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL p : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL cin : STD_LOGIC_VECTOR(3 DOWNTO 1);
BEGIN
h_sum <= a XOR b;
g <= a AND b;
p <= a OR b;
PROCESS (g,p,cin)
BEGIN
cin(1) <= g(0) OR (p(0) AND ci);
inst: FOR i IN 1 TO 2 LOOP
cin(i+1) <= g(i) OR (p(i) AND cin(i));
END LOOP;
co <= g(3) OR (p(3) AND cin(3));
END PROCESS;
sum(0) <= h_sum(0) XOR ci;
sum(3 DOWNTO 1) <= h_sum(3 DOWNTO 1) XOR cin(3 DOWNTO 1);
END df;
What is VHDL program for multiprecision adder?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mpadd is
port ( a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
y : out std_logic_vector(31 downto 0)
);
end mpadd;
architecture mpadd of mpadd is
return std_logic_vector is
Function to_integer(x:in std_logic_vector(6 downto 0))
return integer is
variable sum :integer:=0;
variable Temp :Std_logic_vector(6 downto 0);
begin
temp:=x;
xxx: for i in 0 to 6 loop
if (temp(i)='1')then
sum:=sum+2**i;
else
Sum:=Sum;
end if;
end loop;
return sum;
end function;
variable MaIn : std_logic_vector(22 downto 0); -- Internal Register
variable MbIn : std_logic_vector(22 downto 0); -- Internal Register
variable Ea,Eb : std_logic_vector(7 downto 0); -- Two Exponents including Sign
variable IR : std_logic_vector(22 downto 0); -- Resultant Mantissa
variable IE : std_logic_vector(6 downto 0); -- Resultant Exponent
variable Ns : integer; -- Number Of Shifts
variable Ma,Mb : std_logic_vector(22 downto 0); -- Mangitude Of Two mantissas
variable ES : std_logic; -- Sign Of Resulant Exponent
variable a,b : std_logic; -- Sign Of Two exponents
variable s1,s2 : std_logic; -- Sign Of Two mantissas
variable Sign : std_logic; -- Sign Of Resultant Mantissa
variable W,Z : std_logic_vector(1 downto 0);
variable X : std_logic_vector(31 downto 0); -- Final Result
begin
MaIn:=AccOut(22 downto 0);
MbIn:=Data(22 downto 0);
Ea :=AccOut(30 downto 23);
Eb :=Data(30 downto 23);
a :=AccOut(30);
b :=Data(30);
Z :=(a&b);
case Z is
when "00" => Mb:=MbIn;
Ma:=MaIn;
if((Ea(6 downto 0))<(Eb(6 downto 0))) then
NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0));
for x in 1 to NS loop
Ma := ('0' & Ma(22 downto 1));
end loop;
IE:=Eb(6 downto 0);
Es:=Eb(7)
elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then
NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0));
for x in 1 to NS loop
Mb:=('0' & Mb(22 downto 1));
end loop;
IE:=Ea(6 downto 0);
Es:=Ea(7);
else
NS:=Ns;
Ma:=Ma;
Mb:=Mb;
IE:=IE;
ES:=Ea(7);
end if;
when "01" => Mb:=MbIn;
Ma:=MaIn;
NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0));
for x in 1 to NS loop
Mb:=('0' & Mb(22 downto 1));
end loop;
IE:=Ea(6 downto 0);
ES:=Ea(7);
when "10" => Mb:=MbIn;
Ma:=MaIn;
NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0));
for x in 1 to NS loop
Ma:=('0' & Ma(22 downto 1));
end loop;
IE:=Eb(6 downto 0);
ES:=Eb(7);
when "11" => Mb:=MbIn;
Ma:=MaIn;
if((Ea(6 downto 0))<(Eb(6 downto 0))) then
NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0));
for x in 1 to NS loop
Mb:=('0' & Mb(22 downto 1));
end loop;
IE:=Ea(6 downto 0);
ES:=Ea(7);
elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then
NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0));
for x in 1 to NS loop
Ma:=('0' & Ma(22 downto 1));
end loop;
IE:=Eb(6 downto 0);
ES:=Eb(7);
else
NS:=Ns;
Ma:=Ma;
Mb:=Mb;
IE:=IE;
ES:=Ea(7);
end if;
when others => Null;
end case;
IR:=Ma+Mb;
s1:=Accout(31);
s2:=Data(31);
W :=(s1&s2);
case W is
when "00" => sign:='0';
when "11" => sign:='1';
when "01" => if(Ea>Eb) then
sign:='0';
elsif(Ea sign:='1'; elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'; elsif(Ma sign:='1'; elsif(Ma=Mb) then sign:='0'; else sign:=sign; end if; else sign:=sign; end if; when "10" => if(Ea>Eb) then sign:='1'; elsif(Ea sign:='0'; elsif(Ea=Eb) then if(Ma>Mb) then sign:='1'; elsif(Ma sign:='0'; elsif(Ma=Mb) then sign:='0'; else sign:=sign; end if; else sign:=sign; end if; when others => null; end case; --***********Final Result After Addition*************************** X:=(sign & ES & IE & IR(22 downto 0)); return X; end function; begin process(a,b) begin y<=float_add(a,b); end process; end mpadd;
