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Very Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) is a technology used to fabricate integrated circuits (IC). The various stages of design, simulation, synthesis, timing analysis, layout and fabrication can be discussed in this category. It is a wide spread technology as most of the existing technologies are digital technologies and need an IC to implement. It is VLSI which made computer to be of the size of a pocket from the size of two rooms.
703 Questions
What is VHDL program for 2 to 1 multiplexer?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux2x1 is
Port ( i : in STD_LOGIC_VECTOR (1 downto 0);
s : in STD_LOGIC;
y : out STD_LOGIC);
end mux2x1;
architecture df of mux2x1 is
begin
with s select
y<= i(0) when '0',
i(1) when '1',
'0' when others;
end df;
What is VHDL program for 8 bit priority encoder?
entity priorityenc is
Port ( EI_L : in STD_LOGIC;
I_L : in STD_LOGIC_VECTOR (7 downto 0);
A_L : out STD_LOGIC_VECTOR (2 downto 0);
E0_L : out STD_LOGIC;
GS_L : out STD_LOGIC);
end priorityenc;
architecture Behavioral of priorityenc is
signal EI: std_logic;
signal I: std_logic_vector(7 downto 0);
signal E0, GS: std_logic;
signal A: std_logic_vector(2 downto 0);
begin
process (EI_L , I_L, EI, E0, GS, I, A)
variable j: INTEGER range 7 downto 0;
begin
EI <= not EI_L; -- convert Input
I <= not I_L; -- convert inputs
E0 <= '1';
GS <='0';
A <= "000";
if(EI) ='0' then E0 <= '0';
else for j in 7 downto 0 loop
if I(j) ='1'
then GS<='1';
E0 <= '0';
A<= CONV_STD_LOGIC_VECTOR(j,3);
exit;
end if;
end loop;
end if;
E0_L <= not E0; -- convert output
GS_L <= not GS; -- convert output
A_L <= not A; -- convert outputs
end process;
end Behavioral;
What is the VHDL code to implement NAND gate in behavioral model?
Below code can implement NAND gate in VHDL.
The code is written in behavioral model.
Library ieee;
use ieee.std_logic_1164.all;
Entity gates is
port (a,b : in std_logic; c : out std_logic);
end gates ;
architecture and1 of gates is
begin
process(a,b)
Begin
If (a=1 and b=1) then
C<='0';
Else
C<= '1';
End if;
End process;
End and1;
What is the latest VHDL version?
In 2008, Accellera released VHDL 4.0 to the IEEE for balloting for inclusion in IEEE 1076-2008. The VHDL standard IEEE 1076-2008 was published in January 2009.
Currently, IEEE 1076-2008 is the latest version of VHDL.
What is Bit And Bit vector in VHDL programming?
These are predefined words in VHDL standards. Bit indicates that the data type is a bit i. e. 0 or 1. A bit_vector is an array of bits.
example:
a: in bit;
b: in bit_vector(1 downto 0);
What are the latest research topics in VLSI?
vlsi is nothing but a methodology to design a chip.tremendous openings are there in vlsi (chip desining) field.We have to relate embedded system,dsp,bio-medical applications,cmos desisinging etc....these are all common things related to vlsi ,especially in desining field RTL desining ,STA (ststic timing analysis)
functional verification,power analysis,synthesizer etc...
What is meaning of Test Benches in VHDL?
After compiling a hardware description language like VHDL, it is required to apply inputs to the program in order to obtain out puts. Applying the inputs involves initial conditions. As the systems designed using VHDL are electronic, the initial conditions plays a vital role. Hence, all these conditions along with the information as to where the input is expected to change from 1 to 0 or 0 to 1 is provided to the VHDL program. This is done in the form of a wave or another VHDL program. These are called VHDL test benches. In other words, test benches are the means of applying inputs to VHDL program.
Which crystal structure is preferred to fabricate BJT in VLSI technology?
For MOS fabrication, wafers with crystal orientation <100> are used. This helps achieve a lower threshold voltage and for BJT <111> orientation is preferred.
A VHDL program is written to realize an electronic circuit, system or design. After simulating the code, one needs to dump it into an FPGA or CPLD. This programmable logic device, after dumping, act like the designed system. The inter connections of these devices need to be made as per the code. This means that that a program code which might be logic based now needs to be converted into a physically realizable structure. This involves building a physical structure within an FPGA or CPLD. This process involves converting the VHDL code into a format that can be understood by FPGA or CPLD. Converting our code into 1s and 0s that suit the FPGA or CPLD structure is called synthesis.
Which operator cannot be synthesized by a VHDL synthesis tool?
"&" operator is not synthesized by VHDL synthesis tool.
No single individual, no single company. VLSI was just one of the steps in the process of the industry learning how to squeeze more components on each chip. It is long obsolete.
A CMOS socket is to plug a CMOS transistor into. Alternatively, a CMOS socket is to plug a CMOS integrated circuit into.
CMOS, by the way, stands for, "Complementary Metal Oxide Semiconductor".
What is the effect of frenkel schottky defect on elictrical conductivity?
Both Frenkel and Schotty defects improve the electrical conductivity of an ionic crystal.
Why low power VLSI technology is preferredover VLSI technology?
Low power VLSI is preferred over VLSI.
It is because of the following reasons
- It consumes less power i. e. the power consumption is low
- The power dissipation is also low
- most of the modern devices need to operate at low power
- Complex systems can be designed with reliability as the power consumption is low.
We use modern electronic devices like mobiles ans robotics. These are generally compact and movable. Hence, they operate with a battery rather than power connection. Hence, we need low power operation.
In VHDL, the next statement or command or instance is generally selected using a clock pulse.
clk'event and clk = '1'
means rising edge of the clock.
clk'event and clk = '0'
means rising falling of the clock.
The statement written after this line executes after the occurrence of a rising or falling edge of a clock.
if (clk'event and clk = '1')
The above statement makes the next statement or command to execute for every rising edge of the clock. By applying a clock pulse with minimum time period, we can make the next command to be called.
What the threshold voltage depends on?
The threshold voltage of a device, such as a transistor, depends on its physical structure and material properties, such as channel length, channel doping concentration, oxide thickness, and gate material. It is also affected by external factors like temperature and supply voltage. In digital circuits, the threshold voltage is a critical parameter that determines the device's switching behavior.
What are the types of modeling in VHDL?
VHDL can be written in three different models. They are called
- data flow model
- behavioral model
- structural model
Before attempting a VHDL program, one should know the steps involced in these modeling styles.
Data flow model:
In this model, the input data simply flows into the output. THat is, we will be implementing the relation between input and output terminals directly.
For example,
c < = a and b;
Here, the output c is an ANDing of a and b. We are actually implementing the direct relation between inputs and outputs. That is, c = a + b.
Hence, we need not write any complex conditional statements here in data flow model.
Simply implement the output expression. Thats all.
Here, we are implementing the code at a very basic level i. e. circuit level or gate level.
Behavioral model:
Here, in behavioral model, one needs to code the behavior of the system to be designed. If we consider the same above example, the behavior is that, the output should be one (1) whenever both the inputs are one (1).
we can code it like this:
if (a=1 and b=1) then
c<='1';
else
c<='0';
Or, we can even have the behavior like this:
case s is
when "00"=>c<='0';
when "01"=>c<='0';
when "10"=>c<='0';
when "11"=>c<='1';
We are implementing the LOGIC here. We are least bothered about the circuits that can implement this logic. Hence, it is a system level or logic level modeling style.
Structural modeling:
In structural modeling of VHDL, the concept of components is used. In this model, the system to be designed is considered as a combination of sub structures. These sub structures are called components.
For example, a full adder is a combination of two half adders and an or gate. Hence, the components used for designing a full adder are
- half adder
- OR gate
Initially, these components are mentioned in the architecture of a full adder VHDL program. We call this as component initiation. Then the components are called onto the main program and used. Remember, we are using the functionality of the components in main program but we are not coding them in the main program. The code for the component programs will be present somewhere else in the project. Means, code them once and use them infinite number of times.
What are buried nodes in vhdl?
When implementing a state machine in VHDL, the state variables need to be listed in the port list of the ENTITY section. If not, VHDL considers them as buried nodes and disables the output pins. This means there is no way of using test equipment to look at the machine state.
