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Each data transfer is 3 clock cycles. The first cycle emits address and status, and ALE is used to strobe the low order address. Status is S0, S1, and IO/M- The second cycle sets up the transfer, either floating the data bus for a read, or drving the data bus for a write, and then initiating transfer with RD- or WR-. If READY is not true at the sample point (about the middle of the second cycle) an extra cycle is appended after the second cycle, with all lines frozen, until READY goes true. The third cycle wraps up the transfer. The processor samples data one half cycle before the end of RD- for a read, and it holds the data bus valid for one half cycle after WR- for a write. Up to this point, all cycles are similar. What matters is IO/M-. If high, this is an IO read or IO write; if low, this is a memory read or memory write. However, you have to consider S0 and S1. These are advanced status pins, along with IO/M-, that indicate what the processor is doing. They are emitted at ALE. In addition to indicating IO Read, IO Write, Memory Read, and Memory Write, you can decode Opcode Fetch, Interrupt Acknowledge, and Halt.

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