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Use the link below to go to the data sheet for the IC. On page 5-4 you will see the logic diagram. Using it you can see that A0 - A3 are the address lines used to select the memory location to read from or write to. There are 16 locations. These work in conjunction with the 4 input AND IC's 1-16. These are the decoder section to decode the address and select the memory row. Pin 2 is the Memory Enable pin. This pin enables the memory when it is held low. At the bottom of the page you see the 4 data inputs D1-D4. These are used to input data into memory when the Write Enable Pin (Pin 3) is held low. When the Write enable pin is held high, the data stored at the memory location selected by the address lines will be placed on the outputs. However, the outputs are complemented. So if the data at the selected address is 1001, the output will be 0110. Thus to see the actual data, you would need an inverter on the outputs. So you basically have the address decoder, the memory cells, and the I/O control if you want it in blocks.
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∙ 15y ago
Anonymous
Use as many as you need IC 7489 (memory 16x4 ) and any other digital components/ gates to design and implement a 64x8 memory
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It should actually be a N X 1 Bit RAM, wherein the length of the RAM is N blocks, each block being 1 Bit Wide. I think now, it wont need any more explanation from : Bageshwar P Narain
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Sorry I do not do diagrams
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consider a RAM of 64 words with a size of 16 bits.Assume that this memory have a cache memory of 8 Blocks with block size of 32 bits.Draw a diagram to show the address mapping of RAM and Cache, if 4-way set associative memory scheme is used.
Explain 1-bit ram function with block diagram and truth table?
It should actually be a N X 1 Bit RAM, wherein the length of the RAM is N blocks, each block being 1 Bit Wide. I think now, it wont need any more explanation from : Bageshwar P Narain
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