this question doesn't even freaking make sense, but I know how it feels like to completely and utterly fail at electronics GCSE and go on a surrealist ramble.
either 4 or 8 depending on the type of counter
as flip flop
draw a logic circuit of the clocked SR flip-flop using NOR gate
There are five flip-flops in a five-bit ripple counter.
Clock is propagated from one T or JK flip flop to another hence it works. A ripple counter works by the following principle. A clock pulse is applied to the first flip flop and the output of the first flip flop acts as the clock input to the second flip flop and the sequence continues in that order.
4
A counter is a sequencial circuit with a set of flip flop which counts the number of pulses given at the clock input A counter is a sequencial circuit with a set of flip flop which counts the number of pulses given at the clock input
Designing a 3 bit synchronous counter using jk flip flop is not an easy project for the uninformed. This is best left to professionals who are adept at programming. There are lengthy guides available on the internet if it is necessary to create one.
I am not a Electronic Engineer, so probably any expert out there can correct me if I am thinking wrong.--------- As you can see below there is something common between JK and SR flipflop i.eThe JK flip-flop augments the behavior of the SR flip-flop by interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. Setting J = K = 0 does NOT result in a D flip-flop, but rather, will hold the current state. To synthesize a D flip-flop, simply set K equal to the complement of J. The JK flip-flop is therefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop or a T flip-flop. NOTE: The flip flop is positive edge triggered (Clock Pulse) as seen in the timing diagram.even in the picture they Put SR/RS embeded, that mens JK can work like SR too. I will use this diagram to draw ripple counter. You may note similarity in input output combination too...RS table* We can summarize the operation of the RS-flipflop by the following truth table.R S Q Q' Comment 0 0 Q Q' Hold state 0 1 1 0 Set 1 0 0 1 Reset 1 1 ? ? AvoidJktableand the corresponding truth table is: J KQnext Comment 0 0 hold state 0 1 reset 1 0 set 1 1 toggleDoes that mean we use below coutner 'using 4 bit ripple counter using JK flip flops' as 4 bit ripple counter for RS flip flop too? at the max output states would differ only when both SR/JK is 1 1 ?Figure 1. A Simple Ripple Counter Consisting of J-K Flip-flopsMethod1: You will find answer here: http://www2.cs.uh.edu/~jhuang/JCH/LD/chap07.htmlHere you see how to create ripple counter using RS flip flop. Method 2: create a Toggle function in RS flip flop, then use it in place of typical jk flip flop ripple couters.
The parallel counter incorporates carry lookahead circuits so that all flip-flops in the counter change in sync with the clock pulse. The ripple counter each flip-flop output is the clock for the next flip-flop, causing the most significant bit of the counter to settle only after a long delay time from the input clock pulse.
4. because each flip flop counts to 3
a 2 bit counter is a counter which have only 2 bits i.e. the posibble counting states are 00, 01, 10,11,00. It may also be known as MOD 3 counter. It can be realized by using 2 Flip flop.