How is an instruction fetched from memory into CPU in the 8085 microprocessor?

Answer 1

An instruction fetch in the 8085 is similar to an operand fetch...

During T1, ALE pulses high for one half cycle. On the falling edge, external logic is expected to strobe the AD0-AD7 lines to form the A0-A7 lines. A8-A15, IO/M-, S0, and S1 are also presented, but they stay valid after ALE. S0 is high for opcode fetch, and low for operand fetch. RD- goes true (low) at the end of T1.

If READY is false at the end of T1, TWAIT is entered, and all lines are persisted, with TWAIT repeated as necessary until READY is true.

At the end of T2, the CPU strobes the data presented on AD0-AD7 by external logic.

At the midpoint of T3, RD- goes false (high) and the external logic must stop driving AD0-AD7.

T4 is used to decode and process the opcode. External logic does nothing, since there is no ALE.

If the opcode requires extra data, such as immediate data or an address, T1, TWAIT, T2, and T3 are repeated to fetch the additional bytes, although S0 is low during these cycles.