9,to implement a half adder 5 nand gates and for a full adder,another xor gate is required consisting of 4 nand gates. thus a total of 9 nand gates are required for a full adder.
Check this link http://www.dumpt.com/img/viewer.php?file=bd6b3mqsa66fhr6c76l1.bmp
12 NOR gates are required to implement full adder
4
You cannot design a full adder using only OR gates. You also need AND gates. Typically, this can be done with just NAND gates.
i have the same question. please some1 answer it...
12
A: two
4 as a minimum, but you can use more if you really want to.
A&B = ((A&B)')' So two, it would go a - | ==NAND--=NAND-- b - | By using two NAND gates back-to-back, you can create a normal AND gate.
A full adder can be implemented using a 3-to-8 decoder by using the sum and carry outputs of the adder as the decoder's outputs. Connect the three inputs (A, B, and Cin) to the decoder, which will activate one of its eight outputs based on the binary combination of these inputs. The sum output can be obtained by combining the appropriate activated outputs with XOR gates, while the carry output can be derived using OR gates to combine specific activated outputs. This setup allows the decoder to effectively represent the logic required for a full adder.
ab+bc
As such an OR gate should do the job...but if the question is of using gates other than the simple OR, it should be a combo of NOR and NOT gates; where-in, the NOT gate comes after the NOR gate. Factfully speaking: The output of a NOR gate when fed to a NOT gate shall give you an OR gate. cheers :) Anish Murthy Airpula, RF Design Engineer (F.A.E) Ceramic & Microwave Products Group, Dover Corporation Inc, United States of America