In a computer, cache memory is a special type of fast access memory that is between the CPU and the main memory. If the CPU always had to access main memory, it would spend most of its time idle waiting for that memory to respond. But because memory accesses statistically tend to cluster around each other in real programs instead of completely randomly scattering across memory, a single CPU memory access can cause the cache memory controller to perform a fast burst access of main memory including that address to load an entire "line" of cache memory. If a following CPU memory access is in this same "line" of cache memory that has already been loaded, it will not have to wait for the main memory to respond, instead the cache responds first providing the copy it has of that address' contents.
Cache memory was originally invented in the late 1950s by IBM for their 7030 Stretch supercomputer (a machine built entirely using discrete germanium transistors, no integrated circuits at all). However all the 7030 documents use the term "virtual memory" for what is now universally called cache memory, and "virtual memory" means something entirely different now.
Each cache memory unit is composed of three sections:
Cache memory is organized into levels (L1, L2, L3, etc.) with the L1 Cache closest to the CPU and each additional level further away until the final Cache level connects directly to the memory. The L1 Cache uses the fastest speed SRAM but has the smallest amount of SRAM and each additional level uses slower speed SRAM but has more SRAM than the previous level. The L1 Cache is usually divided into two independent Caches (L1 Instruction Cache and L1 Data Cache) and is dedicated to supporting only one CPU but each additional level is usually a single Cache (shared by both instructions and data) and in systems having multiple CPUs may be shared by two or more CPUs. In systems having multiple CPUs the cache controllers must implement special bus protocols to coordinate line invalidations and updates to prevent some of the CPUs from accessing obsolete Cache contents from its Caches when a different CPU that does not use those Caches has modified memory that is mapped to both its local Caches and the other CPUs local caches.
Proper design of a Cache memory system for a computer requires extensive simulation of typical real code expected to be used on the system. Any problems found must be corrected, so that the Cache usage will remain even and balanced, and anticipated performance verified.
Between a computer's CPU and its main memory there are as many as three levels of Cache Memory. Level 1 cache is typically a small section of very, very fast memory right on the CPU chip. It is designed to work with the CPU without slowing it down. Most CPUs now also have a second section of memory, level 2 cache, which is larger, and holds a few pages of virtual memory that the CPU "expects" will be needed next. Some CPUs even have level 3 cache on-chip, but off-chip level 3 cache is more common. Level 3 cache is often large enough (one MB or a few MB) that an entire program and its data might fit in cache, so the whole program runs without making further use of the main memory (the 2 or 4 or 8 GB of "system RAM").
All of these are faster than main memory. Judicious use of them by the CPU helps maintain its ability to run at top speed.
High speed memory that reside between the microprocessor and RAM in a computer.
Allows a processor to access data more quickly.
The role of the cache memory is to store the data that is used frequently in the main memory to increase the speed of the process..
There are different type of cache memory: processor cache memory, cache memory ram,1 cache memory l2, cache memory, CPU cache memory, disk cache memory, hard disk cache, cache memory motherboard.
There are different type of cache memory: processor cache memory, cache memory ram,1 cache memory l2, cache memory, CPU cache memory, disk cache memory, hard disk cache, cache memory motherboard.
No cache memory is not visible.....
Register memory are smaller in size than cache memory and registers are faster than cache..Cache memory store the frequently used data from main memory..
sram is used for cache for cache memory.
The maximum size of a cache memory is theoretically equal to the amount of primary memory(RAM).Like Cache only memory architecture where the whole memory space is filled up with the cache only.
Cache Memory is needed because Hardware implements cache as a block of memory for temporary storage likely to be used again.
Cache memory is smaller and quicker, primary memory larger and slower.
memory cache is on memory RAM, disk Cache is on the hard drive. They make things to get faster. For instance Google Earth use this disk cache to show you offline images.
l1 cache l2 cache
cache memory is neither main memory nor second memory. DDR's are Main memory and Disk is second memory.
because cache memory is costlier than main memory and physical size of cache memory also matters.ignoring the cost , if we use large cache memory, it will take larger physical space.so mother board won't be able to accomodate it