Special restart instruction used with interrupts
There are 74 instructions in the 8085 microprocessor.
The 5.5 in RST 5.5 means that the interrupt vector is located between RST 5 and RST 6.
The RST instruction is a 1 byte opcode with a 3 bit imbedded operand. There are 8 different RST instructions. Each pushes the PC on the stack, and loads the PC with the operand's value times 8. (0H, 8H, 10H, 18H, etc.)Pushing the PC on the stack and loading a new value into the PC is exactly what a CALL instruction does, so the RST instruction is a 1 byte CALL instruction. The difference between RST and CALL is that CALL is a 3 byte instruction which can go anywhere in memory in one instruction.
The lowest priority interrupt in the 8085 microprocessor is INTR, unless you also consider the software interrupts, RST 0 through RST 7, which are even lower.
We can implement "Divided by '2' " operation by using RRC.
RST is simply the opcode chosen to represent the Restart instruction.
The name, RST6.5, was chosen because the interrupt vector lies halfway between RST 6 and RST 7, specifically at address 0034H.
In 8085 program counter stores the address of the next instruction which is to be fecthed.same function is performed by instruction pointer in 8086.
The 8085 has five interrupts, INTR, RST5.5, RST6.5, RST7.5, and TRAP. It also has eight software interrupts, RST0, RST1, ..., RST7. The INTR interrupt requires a hardware response that is an opcode. Usually, the opcode is either a CALL instruction, in which case the interrupt vector can go anywhere in memory, or it is an RST instruction, in which case the vector is based on a table in low memory. In the case of RST instructions, either directly or via INTR, or the RSTx.5 interrupts, you simply multiply the interrupt number by 8 to get the vector address. The following table presents the vector addresses for all possible interrupts... RST 0 - 00H RST 1 - 08H RST 2 - 10H RST 3 - 18H RST 4 - 20H TRAP - 24H RST 5 - 28H RST5.5 - 2CH RST 6 - 30H RST 6.5 - 34H RST 7 - 38H RST 7.5 - 3CH
20H
RST 5.5 is level triggered interrupt & maskable also. it can be masked by using SIM intrruction. Vector address of the RST 5.5 interrupt is 002Ch
No. They have a different instruction set. However, the processors are sufficiently similar that an 8086 assembler could assemble an 8085 program, given appropriate constants and macros. Some things, however, such as RIM, SIM, RST, etc. do not have equivalents in the 8086.