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For bulk memory-to-memory copy, the main bus bandwidth will dominate, and the other components must be able to keep up (to saturate the bus and the storage components behind it).

For single-byte random reads, latency will dominate. We want read requests put on the main bus to be satisfied with low latency, but inevitably several CPU cycles will go past (stalls will happen) before the request is satisfied. A larger cache may be able to reduce the number of such requests, but the cache hit ratio is very very sensitive to the application workload, and in the worst case we will see a low cache hit ratio with extra latency while we suffer the expense of a large cache.

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Q: What is the relationship between a computer's CPU speed CPU cache and it's main bus speed with regard to the computer's performance?
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