What is race condition in flip-flops?

Answer 1

A race condition occurs when the output of a logic circuit is fed back into the input in such a way as to change the output, such that settling of the inputs delays the final stabilization of the outputs. It can also occur when two inputs to a circuit change at the same relative time, but the result depends on time sequence, such as in a D-FlipFlop where the clock is edge triggered.. In a full adder, for instance, propogation of carries can delay the final output, resulting in performance (speed) degradation. That is why many full adders have look-ahead carry logic. In essence, to avoid a race condition, you want to design the circuit so that propagation delay does not accumulate in series. A striking example in my memory was where an 8085 microprocessor system used WR/ to drive the databus drivers, while at the same time using WR/ to strobe the destination latches. That was a race condition, and it made the final contents of the latches indeterminant.

Answer 2

A race condition in any logic circuit is where two inputs change at about the same time, making the output indeterminate.

That said, a race condition in an S-R flip flop is where both of the S and R inputs go false at the same time. As a result, the output is indeterminate.

In order to avoid race conditions, you need to ensure that all setup and hold times are maintained as designed by the particular device, and that you include adequate design for transmission line effects, i.e. capacitance and inductance versus resistance.

Answer 3

race-around condition :- (taking JK- flip-flop)

well we know that in a JK flip-flop the outputs are again fed back to the inputs.Now, let us consider a situation that for J=K=1 the previous state(Q1) of flip-flop get toggled (inverted) giving next state(Q2=Q1'). let us assume that the value of the clock - pulse didn't change even after the state conversion, this means the flip - flop is still in ON mode for the same values of J and K , so the flip-flop again toggles the present state i.e. Q2 gets toggled , now Q3=Q2'=Q1 . This process continues over and over till the clock pulse changes . This continuous undesirable transitions of outputs for the same clock-pulse is called race-around condition.

steps to avoid :-

1. to avoid this condition the time period of the clock pulses must be less than the propagation delay through the flip-flop.

sole dependence of propagation delay should be avoided as it is difficult to control it to obtain the above condition the flip-flop must be provided with some external mechanism or circuit that adds extra delay.

2. An even better approach is to design circuitry that makes the flip-flop sensitive to clock-pulse transition instead of clock-pulse duration .This idea brings the concept of edge-triggered flip-flops.