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To design an OR using 2:1 mux, we need to tie the "First" input to "Logic 1″ and the "Zeroth" input to the one of the input of the OR Gate. The other input of OR gate would be connected with the select line of the MUX.
Now, the output of the MUX would be "1″ when any oth the two inputs would be "1″ otherwise it would be "0″ for all conditions.
Wiki User
∙ 13y ago
Wiki User
∙ 12y agoSET:
S = A
I0 = B
I1 = 1
So, Y = S'.I0 + S.I1
Y = A'.B + A.1
Y = A'.B + A
Y = (A+A').(B+A)
Y = 1.(B+A)
Y = A+B
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What is an OR gate?
An OR gate is a digital logic gate. If one or both of the inputs to the gate are "1", then the ouput of the gate will be "1" . If both of the inputs to the gate are "0" then the output of the gate will be "0".
What gate produces a 0 if all its inputs are 1 and a 1 otherwise?
A NAND gate.
How to convert nor GATEto not gate?
This is made by joining the inputs of a NOR gate. As a NOR gate is equivalent to an OR gate leading to NOT gate, this automatically sees to the "OR" part of the NOR gate, eliminating it from consideration and leaving only the NOT part. Truth Table Input A Output Q 0 1 1 0
When is that the NA ND logic gate can function as a NOT logic gate?
The NAND gate has two or more inputs, and one output. This output is the complement of the AND of all the bits and will only be 0 if all the inputs are 1.A NOT gate on the other hand has only 1 input, and the output is the complement of this input.So to make a NAND gate into a NOT gate, we should tie (short, connect to same value) all the inputs of the NAND gate. At the output we would have the complement of the signal given at the tied inputs.This way we have a NOT gate from a NAND gate.
What logic gate might be called the all or nothing gate why?
AND gate is called an all or nothing gate.Because it produces a 1 only in one case when all its inputs are "1". In all other cases its output is a "zero".
How you design NOR gate using 2 1 mux?
If you want to have output z = A NOR B. Make select line of 2X1 MUX = A. Now, the first i/p line (corresponding to A =0) = B ' BAR tthe second i/p line (corresponding to A=1) = 0.
Can inverter circuit be design from multiplexer circuit?
MUX(A, B, S) = A*S + B*S' NOT(A) = MUX(0, 1, A) = 0*A + 1*A' = A' From http://noyesno.net/
How Design a 3 input AND gate using 2 by 1 Multiplexer only?
help
A 4 variable logic expreSSion can be realized using which multiplexer?
using 8:1 mux....
What are advantages and disadvantages of multiplexer?
Advantages are 1: it reduces number of wires. 2:it reduces circuit complexity and cost. 3:it simplifies logic design. 4:we can implement many combinational circuits using MUX. 5:it does not need kmaps and simplification.
How is half adder implemented using null convention logic?
by using 4 NCL gates we can design or implement a half adder.gates used in half adder are TH12[1 GATE],TH22[1 GATE] and TH24COMP0 [2 GATES].this NCL have a concept of DUAL-RAIL.output we get for this are S0,S1,Cout0,Cout1.
Carry in a half adder can be obtained using which gate?
OR Gate - Hemanth The carry is generated only when 1 and 1 is added. So it should be AND gate and not OR. Maxim Tellis
What is difference between Mux and Routers?
a mux has many i/ps & 1 o/p but a router connects many n/ws and the may or may not be of same kind a mux does not follow an algo but router follows algo such as dikakstra bellman ford or any other or a combination.......
Can you implement higher order mux from lower order.how?
yes, given MUX in number To be implemented MUX 2:1MUX x 3 4:1MUX 4:1MUX x (4+1) 16:1MUX 4:1MUX x (16+4+1) 64:1MUX 8:1MUX x (8+1) 64:1MUX 8:1MUX x (32+4+1) 256:1MUX
How do you design 1-bit half adder with NAND gates only?
As this is obviously a homework problem, I won't answer it. However I will give you couple of hints. First figure out how to make an exclusive-or gate from nand gates. The rest is trivial. Using a Karnaugh map will make it much simpler to design than using an ordinary truth table.
Design a 4 bit majority gate circuit whose output is 1 if the majority of the input are 1 and output is 0 why?
4000 yrs
How do you construct 16x1 multiplexer circuit using 8x1 multiplexer using diagram?
You'l need 5 4 to 1 muxes for making a 16 to 1 mux if your inputs are say W(0)-W(15) i.e 16 inputs ..... you start of with giving 4 inputs each to the 4 to 1 muxes the select lines for all 4 4 to 1 muxes will be common now each of the four 4 to 1 muxes is giving you one o/p so ..... take each of those 4 outputs and give them to the fifth 4 to 1 mux and voila you have a final o/p corresponding to 16 inputs !!! THIS IS HOW IT WILL LOOK LIKE inputs outputs mux 1 : w(0)w(1)w(2)w(3) m(1) mux2 : w(4)w(5)w(6)w(7) m(2) mux3 : w(8)w(9)w(10)w(11) m(3) mux4 : w(12)w(13)w(14)w(15) m(4) taking the above 4 outputs and giving them 2 mux5 mux5 : m(1)m(2)m(3)m(4) m(5) m(5) is the final output corresponding to 16 inputs W(0)-W(15)
