1. Fetch
2. Decode
3. Execute
RET instruction needs 3 machine cycles. One to fetch and decode the instruction(4 T states), and two more machine cycles(i.e. 2*3=6 T states) to read two bytes from the stack(stack is exterior to microprocessor, stack is in R/W memory, so to exchange data with stack needs machine cycles). Thus, RET instruction needs total 3 machine cycles and 10 T-states.
There are three fetch cycles in a three byte instruction. The first one is four clock cycles long, while the other two are three clock cycles long. Depending on what the instruction does, there will then be more read/write cycles.
when conditional jump instruction is executed it has 10 m/c cycles bt when nt executed it has 7 m/c cycles....while unconditional jump instruction has 10 m/c cycles...
4. 3 to fetch, and 1 to decode/process.
CALL, requiring 18 clock cycles.
an instruction cycle may consist of a number of machine cycles.
The CALL instruction uses 18 clock cycles. 3x3 fetch, 2x3 store, 1x1 decode, 2x1 decrement.
The OUT instruction on the 8085 uses 10 T cycles, 3 for opcode fetch, 1 for opcode decode, 3 for port address fetch, and 3 for port data store. Any wait states encountered are above and beyond that.
3 for opcode fetch, 1 for opcode decode, 3 for operand fetch, and 3 for opcode store, for a total of 10, not including wait states.
Depending on the particular microprocessor, a machine cycle is the fetch or store of one (typically, one byte) native word. In the 8085, this is a byte fetch or store, plus the overhead in decoding and processing the instruction. In this case, the first machine cycle is four clock cycles, or T states, and subsequent machine cycles are three clock cycles, although certain instruction sequences, such as DAD, require two extra clock cycles.
The SHLD instruction in the 8085 requires 6 (opcode, decode, and increment) + 3 (low address fetch) + 3 (high address fetch) + 3 (low, L, store) + 3 (high, H, store) cycles which equals 18 cycles, not including wait states.
Summary − So this instruction XCHG requires 1-Byte, 4-Machine Cycles (Opcode Fetch) and 4 T-States for execution as shown in the timing diagram.