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Its simple exclusive or gate b/e x, y (any thing a,b etc..) combined with another exclusive or gate of z. i was trying to past a pic...but this sheet does not allow.....

x----`````

! ! `----

y----```` -

----- `````

----- !! `------------

z--------------- `````

suppose if we apply 010 to xyz, then XOR of xy (01) is 1 then XOR of previsou 1 (xy) and z is again 1 which is output,....so to make even 1's we 'll add 1....

another example lets take input 101...then XOR of xy (10) is 1 and XOR with z (1 with Z) that is 1 and 1 is zero which means that input 1's are already even so no additional 1 is needed.

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14y ago
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10y ago

Only 8 NAND gates would be needed. 4 for A,B and 4 for the output of the previous and C.

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Q: A circuit diagram for a 3 bit parity generator with only NAND gates used?
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