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Consider a 16 bit microprocessor with a 16 bit external data bus driven by an 8 bit MHz input cycleswhat is maximum data transfer rate across the bus that this microprocessor can sustain?
Wiki User
∙ 14y ago
Minimum bus cycle duration = 4 clock cycles Bus clock = 8 MHz Maximum bus cycle rate = 8 M / 4 = 2 M /s Data transferred per bus cycle = 16 bit = 2 bytes Data transfer rate (per second) = Bus cycle rate * data per cycle = 2 M * 2 = 4 M bytes per second
Wiki User
∙ 15y ago
Wiki User
∙ 14y agoThe 8086/8086 has a basic cycle of four clock cycles, in which it can read or write one word. Assuming that an instruction could setup a stream of data transfers, then two bytes could be transferred per each 4 cycles. With an 8 MHz clock, each cycle is 125 ns, so two bytes could be transferred each 500 ns. This is a transfer rate of 4MB/s.
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Consider two microprocessors having 8 and 16bit wide external data buses respectivelyThe two processors are identical other wise and their bus cycles take just as longsuppose all instructions?
During a single bus cycle, the 8-bit microprocessor transfers one byte while the 16-bit microprocessor transfers two bytes. The 16-bit microprocessor has twice the data transfer rate.
What is data transfer scheme?
Data transfer schemes in Microprocessor :-Data can be transferred between memory, microprocessor and input output devices. the speed and format of all the input output devices does not matches microprocessor.For example some input output devices like ABC' and DAC's are slow as compared to microprocessor.Some devices are serial in nature while microprocessor is parellal in nature.Because of this, number of data transfer schemes have been devided to cope with this problem.The data transfer schemes can be broadly clasified into two categories :-
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