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____

____ c ----->|xor |------------> s

a ->|xor |-+------------>|____|

b ->|____| | _____ _____

+--->|nand |------>|nand |--> c

c ----->|_____| +-->|_____|

_____ |

a ----->|nand |--+

b ----->|_____|

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12y ago
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14y ago

First of all, NAND and NOR gates have been proven to be logically complete. That means you can create every other logical gate with just NANDs or just NORs. Other gate functions are XOR, AND, OR, NOT, etc.

To clarify: The notation I am using is [NAND] represents the NAND gate. Having A,B means the two inputs are A and B. If there is just one input, then that input gets mapped to both inputs. The '|' is supposed to show a junction between two lines. '-' is a single line and '=' is a double line. The '. . .' is just empty space, trying to keep the diagram intact.

Some NAND designs we will need are:
AND: A,B--[NAND]==[NAND]-->out

OR: A--[NAND]--|==[NAND]--out
. . . .B--[NAND]--|

first NAND connects to top and bottom NANDs
last NAND has inputs taken from output of the middle two NANDs
. . . . . . . . . . . . . . . A--|[NAND]---|
XOR: A,B--[NAND]------| . . . . . . . |===[NAND]--out
. . . . . . . . . . . . . . . B--|[NAND]---|

Sorry if the diagram is difficult to follow.


The second part is what a full adder is. A full adder is a system that takes in three signals and outputs two. The three input signals are A, B, and Cin. The two outputs are S and Cout. The point of a full adder is that you can cascade them. The Cout of the first becomes the Cin of the second. That way you have a general one bit adder, but can make an N bit adder by stringing cascading them. So the first step in creating a full adder is writing out the truth table, a table where inputs get mapped to specific outputs. I am going to use '-' in place of spaces so the spacing stays the same after I post.

Input- - - - - - - - - - - - - - - -Output
A - - B - - Cin - - - - - - - - - S - - Cout
0 - - 0 - - 0 - - - - - - - - - - -0 - - 0
0 - - 0 - - 1 - - - - - - - - - - -1 - - 0
0 - - 1 - - 0 - - - - - - - - - - -1 - - 0
0 - - 1 - - 1 - - - - - - - - - - -0 - - 1
1 - - 0 - - 0 - - - - - - - - - - -1 - - 0
1 - - 0 - - 1 - - - - - - - - - - -0 - - 1
1 - - 1 - - 0 - - - - - - - - - - -0 - - 1
1 - - 1 - - 1 - - - - - - - - - - -1 - - 1

It can be seen that S = [A XOR B XOR Cin]
It can be seen that C = [(A AND B) OR (A AND Cin) or (B AND Cin)]
or equivelently (and more efficiently) C = [(A AND B) or (C AND (A XOR B))]

Its probably not completely obvious at first, but using Karnaugh maps or other techniques you get this result.

So now it is just a matter of replacing each gate (XOR AND OR) with its correspdonding NAND system. Although I am sure it would be quite a feat to put that diagram up on here using text symbols, I feel that I am not up for that rather large task, haha. Hope this answered your question or helps lead you in direction you are looking for.

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15y ago

You can find a drawing of a half adder here: http://www.dumpt.com/img/viewer.php?file=bd6b3mqsa66fhr6c76l1.bmp

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Q: Draw the logic circuit for a haly adder using nand gates only?
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