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You can address 214 or 16384 different locations with 14 address lines.
It depends on how wide the data buses are on each chip, and how they're connected. If they're one byte wide, you could need over 256 million addresses, one for each byte. if they're wider, and connected to show an even wider combined data bus, it could be much less; around 32 million.
16KB
Usually high speed SRAM with CAM (content addressable memory) line address tags.
2N
A 16 bit address bus can select 65536 locations.
When CPU needs to access a memory location for read or write, it places an address on the address bus. In case of Read, data is meant to be read into Memory Data Register (MDR) and in case of Write, the data (to be written to memory) is put in the MDR.After that CPU issues the Read or Write signal.However, CPU needs to know when the desired memory function (Read or Write) has been completed..This line back to the CPU saying that the operation is complete is sometimes called memory function complete (MFC).In the meanwhile, the instruction or step that is executed by the CPU is known as Wait for Memory Function Completed (WMFC)To summarize:To read (if you are a CPU): Put the desired memory address in the MAR.Assert the Read control line.Wait for the MFC line to be set to 1 by the main memory unit. (Or wait for the appropriate amount of time, if there's no MFC line with your particular main memory unit you are using (rare these days).)Get the data out of the MDR.To write (again, if you are a CPU): Put the desired memory address in the MAR and put the desired data in the MDR.Assert the Write control line.Wait for the MFC line to be set to 1 by the main memory unit
When CPU needs to access a memory location for read or write, it places an address on the address bus. In case of Read, data is meant to be read into Memory Data Register (MDR) and in case of Write, the data (to be written to memory) is put in the MDR.After that CPU issues the Read or Write signal.However, CPU needs to know when the desired memory function (Read or Write) has been completed..This line back to the CPU saying that the operation is complete is sometimes called memory function complete (MFC).In the meanwhile, the instruction or step that is executed by the CPU is known as Wait for Memory Function Completed (WMFC)To summarize:To read (if you are a CPU): Put the desired memory address in the MAR.Assert the Read control line.Wait for the MFC line to be set to 1 by the main memory unit. (Or wait for the appropriate amount of time, if there's no MFC line with your particular main memory unit you are using (rare these days).)Get the data out of the MDR.To write (again, if you are a CPU): Put the desired memory address in the MAR and put the desired data in the MDR.Assert the Write control line.Wait for the MFC line to be set to 1 by the main memory unit
The differences among direct mapping and set-associative mapping :Direct mapping : Each line in main memory maps onto a single cache line.Set-associative : Each line in main memory maps onto a small (collection) set of cache line.Direct mapping : A memory block is mapped into a unique cache line, depending on the memory address of the respective block.Set-associative : A memory block is mapped into any of the line of a set. The set is determined by the memory address, but the line inside the set can be any one.dont knowyet
The differences among direct mapping and set-associative mapping :Direct mapping : Each line in main memory maps onto a single cache line.Set-associative : Each line in main memory maps onto a small (collection) set of cache line.Direct mapping : A memory block is mapped into a unique cache line, depending on the memory address of the respective block.Set-associative : A memory block is mapped into any of the line of a set. The set is determined by the memory address, but the line inside the set can be any one.dont knowyet
2^14 memory locations. In general for n-bit address bus, its 2^n
Read From Memory Steps1 Processor signals the memory to be read on to address bus.2 Specific memory chips that hold the memory location are made ready.3 Chip select is generated.4 A delay is added to allow the memory to settle and to be available to read.5 Data is placed on to the data bus.6 Control unit turns on the read line on control bus.7 Data is placed on to the (MDR) memory data registry