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This question should be more specific so that someone can more easily and accurately assist you. However, i will attempt to answer your question assuming that your are asking about the L1, L2, and L3 cache memory types.
L1, L2 and L3 (or level 1, level 2 and level 3) are different memories seperate from the processor, but it is the memory more easiest and quickly accessible by the processor, or cpu. These memories are used by the processor to store common instructions, images..etc. so that it can easly and quickly access it whenever required to. First the processor checks the L1 cache memory (usually the level with the lowest amount of memory), if it doesn't find what it needs there then it searches through the L2 and then L3.
If what the processor needs isn't in the cache memory, then it will check the HDD and RAM.
Wiki User
∙ 9y ago
Wiki User
∙ 12y agocache memory type is three L1,L2,L3means level1,level2,level3
L1 use for processor
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Does some CPUs now have three levels of cache memory?
yes
What cache typically has the most memory?
Caches are generally defined as L1, L2, and L3. If a CPU has any cache memory at all, it will have at least L1 cache. L1 cache is the fastest, and most expensive, type of cache memory. Usually CPUs will only have a very small amount of L1. L2 is typically larger, less expensive, and slower than L1. L3 is less expensive, larger, and slower than L1 or L2, if present. All three levels of cache memory are magnitudes faster than system memory. Systems withequivalenthardware, including CPUs will identical speeds, will perform better at certain tasks when more cache memory is present, with L1 cache adding the most performance boost.
For a direct- mapped cache a main memory address is viewed as consisting of three fields.List and define the three fields.?
Tag Slot and Offset
What is meant by cache memory?
In a computer, cache memory is a special type of fast access memory that is between the CPU and the main memory. If the CPU always had to access main memory, it would spend most of its time idle waiting for that memory to respond. But because memory accesses statistically tend to cluster around each other in real programs instead of completely randomly scattering across memory, a single CPU memory access can cause the cache memory controller to perform a fast burst access of main memory including that address to load an entire "line" of cache memory. If a following CPU memory access is in this same "line" of cache memory that has already been loaded, it will not have to wait for the main memory to respond, instead the cache responds first providing the copy it has of that address' contents.Cache memory was originally invented in the late 1950s by IBM for their 7030 Stretch supercomputer (a machine built entirely using discrete germanium transistors, no integrated circuits at all). However all the 7030 documents use the term "virtual memory" for what is now universally called cache memory, and "virtual memory" means something entirely different now.Each cache memory unit is composed of three sections:cache controllercontent addressable memory (CAM)fast access static random access memory (SRAM)The cache controller section contains all the logic circuits that coordinate the operation between the CPU(s), cache, and main memory. The CAM is a special type of memory used to store the memory address of each active cache "line" along with some status bits that is addressed by it contents (not an address number as in ordinary RAM and ROM). The SRAM contains the copies of address contents previously read from main memory, and is addressed through the CAM. Cache memory is organized into levels (L1, L2, L3, etc.) with the L1 Cache closest to the CPU and each additional level further away until the final Cache level connects directly to the memory. The L1 Cache uses the fastest speed SRAM but has the smallest amount of SRAM and each additional level uses slower speed SRAM but has more SRAM than the previous level. The L1 Cache is usually divided into two independent Caches (L1 Instruction Cache and L1 Data Cache) and is dedicated to supporting only one CPU but each additional level is usually a single Cache (shared by both instructions and data) and in systems having multiple CPUs may be shared by two or more CPUs. In systems having multiple CPUs the cache controllers must implement special bus protocols to coordinate line invalidations and updates to prevent some of the CPUs from accessing obsolete Cache contents from its Caches when a different CPU that does not use those Caches has modified memory that is mapped to both its local Caches and the other CPUs local caches.Proper design of a Cache memory system for a computer requires extensive simulation of typical real code expected to be used on the system. Any problems found must be corrected, so that the Cache usage will remain even and balanced, and anticipated performance verified.
What is processor cache memory?
Processor cache is intermediate memory between the processor itself and main memory (RAM). Because processors can read data so much faster than main memory, the speed of a processor would essentially be limited to the speed of RAM if we couldn't find a way to increase the efficiency of accessing data in main memory. Caches, which have a much lower access time than RAM, help to mitigate this problem. Caches work on the principle of spacial locality. That is to say, they use the idea that if you access a location in main memory, then it is highly likely that the next memory location you want to access is very close to where you are. When you access main memory, the cache will actually pull in a "chunk" of data (often called a "cache line") in the hope that the next time you try to access data it will already be in the cache. Typically there are two levels of cache (though with the increasing popularity of multi-core processors, three levels of cache are becoming more and more necessary). The first level of cache (L1 cache) is what is directly accessed by the processor and is therefore the fastest (and most expensive) cache. L1 cache is usually split into two parts: data cache and instruction cache. The instruction cache holds the instructions of running programs that the processor needs to execute. The data cache holds the data being used by current instructions. The second level of cache (L2 cache) is where the L1 cache pulls in information from. L2 cache is slower than L1 cache, but is more affordable and can be much larger than L1. With the exception of L3 caches mentioned above, this is the cache which pulls information in from main memory.
What are the difference between iconic memory and echoic memory?
duration of iconic memory for about less than one second whereas duration of Echoic memory for about Three to four second- Nilesh Gunjal ( M.A. Psychology)
What are three things you can do to improve slow browser?
Clear cache memory delete temporary internet files and cookies decrease CPU usage
Three cache mapping techniques?
Three types of mapping procedures are there? (1) Associative Mapping-The fastest and most flexible cache organizations uses associative mapping. The associative memory stores both the address and content of memory word. This permits any location in catche to store word in main memory. (2) Direct Mapping-Associative memories are expesive compared to RAM's because of added logic associated with each cell. (3) Set Associative Mapping-It is a more general method that includes pure associative and direct mapping as special case. It is an improvement over the direct mapping organization in that each word of cache can store two or more words of memory under the same index address. Each data word is stored together with its tag and the number of tag data items in one word of cache is said to form a set. With Regards Veer Thakur Chandigarh
What is the difference between the three types of ballistics?
What is the difference between the three types of ballistics
What is the difference in size in an iPhone 2g and an iPhone 3g?
There is no difference in VISUAL size between the two. The difference is the gigs. Each gig has one milion bites of memory and so the iPhone 2g has two million bites of memory and the iPhone 3g has three million bites of memory. It sounds pretty complex, I guess you could say, but it really isn't.
What is the difference between a horse?
The difference between a horse is about three feet.
What is the difference in weight between a rabbit and hippo?
Three tons is the difference between them
