X1 and X2 are connect to a crystal.
The CLK signal in the 8085 is the system clock, which is the External Input Frequency or Crystal divided by two. It can be used to develop bus control logic, because it is essentially the inverse of ALE for one half clock cycle.
Early microprocessor neded clock input to be given externally, i.e. an extra clock generator chip is necessary. the clock generator chip had two pins between which a crstal or an RC circuit could be connected for the generation of basic frequency desired. however, microprocessor, that were designed after 1978(Intel 8085, M6809, etc.) had the clock generator circuit embedded in the microprocesor chip.
The READY signal of the 8085 microprocessor is sampled approximately one half clock after the trailing edge of ALE and, if not asserted, repeatedly one full clock cycle later until it is asserted.
S0,S1 and IO/M are the status signal of 8085 mpu
The HOLD pin indicates that an external device wants the 8085 to stop and allow the external device to drive the bus. The acknowledge of control transfer is HLDA, however, it is important to note that HLDA does not mean the current cycle is complete - it means that the current cycle is the last cycle, at which point the 8085 will release the bus. (One half clock cycle later.)
The crystal frquency in an 8085 system is twice the desired clock frequency, so a crystal of 2.2 MHz is required to operate at 1.1 MHz.Note: Clock frequency is not the same as instructions per second, because the instructions in an 8085 take a variable number of clock cycles, between 4 and 18, to execute.
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The clock out frequency of an 8085 is one half the crystal frequency. The period of one T cycle is the inverse of the clock frequency. At a crystal frequency of 5MHz, the clock is 2.5MHz, and T is 400 ns.
(Except for my discussion of ALE, below, I was not aware that the clock signal in the 8085 microprocessor was not perfectly square, but in my designs using the 8085 it did not matter, as I always made sure the hardware design always met the correct setup and hold times. This answer is intuitive, rather than being based on internal design knowledge.) In order to maximize clock speed, and resulting processor performance, Intel designed internal delays into various aspects of the 8085 design. Since these delays were not symmetrical for each edge of the clock, the resulting clock is not square, even though it is stated that clock is one half of the oscillator frequency. (As far as ALE is concerned, I was aware that ALE became true about one sixth of a clock after the falling edge of clock, and persisted for about one half clock. This does not line up with clock or with the oscillator running at twice clock, so it is obvious that there are internal delays built in. All I knew was that the rising edge of clock following ALE occured during ALE, and that the status lines and high address bus changed state about one sixth clock after the beginning of ALE, so I took this into account when I designed my bus control logic.)
8 bit input is given to Intel 8085 microprocessor.
There are no instructions in the 8085 that execute in only one clock pulse. The minimum number of clock cycles is four; three for instruction fetch and one for instruction decode/execute.
The READY pin on the 8085 microprocessor is used to delay the completion of a bus transfer cycle. It is sampled by the 8085 at the falling edge of clock following ALE. If it is high, the cycle completes. If it is low, the cycle is extended by one clock, with all lines held steady - then it is sampled again at each of the next falling edges of clock until it is high. The purpose of READY is to allow (usually) memory devices to operate at a slower speed than the 8085.