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- An MMU (memory management unit) generates physical address.
- A CPU (central processing unit) generates a logical address.
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What kind of memory addresses does a memory management unit generate?
- An MMU (memory management unit) generates physical address. - A CPU (central processing unit) generates a logical address.
What characteristics of the motherboard architecture determine the amount of memory that a CPU can address?
RAM and the memory cache
How does CPU generate logical address?
Lets take the scenario of CPU MMU (memory management unit) Physical Memory.CPU generates the logical address as Page number + Page offset.Of course this address will point to some physical address.Page number is for the index in page table (for base address).The base address + offset is sent to MMU which is mapped to the corresponding physical page.
What is the difference between Harvard and Princeton computer architecture?
Harvard architecture : _________ ______ | code | | | | memory | | CPU | <-----> |_________| | | | | ----------- | data | | memory | ---------------- the CPU generated address is either point to code or data memory. Princeton arhitecture: data memory <--------> CPU <-------> code memory in this the CPU generated address will point to both the data and code. for this some internal operation are take place to point to either data or code. answered by prasad. mail prasad40613@gmail.com
Which 3 computer devices generates heat?
The folowing 3 devices generate heat:hard disks, memory, and CPU's
What is the memory's addressibility?
HI I am Ahtarva,The addressibility is how many bits does that particular processor or micro-controller's architecture use to specify the address of a memory location in the memory. For example if someone say that addressibility is 8 bit then your memory address contains 8 bits and at maximum you have 2^8 different memory locations (or say memory addresses in your device). Here 2^8 is called Address space.
What is the function of the control unit in the CPU?
The control unit provides the timing and control signal to all operations of microcomputer. It control the flow of data between microprocessor and memory and peripherals.
When evaluating CPU memory do you check the cache memory?
The only memory on the CPU is cache memory and it is only dependent on the CPU type and generation you use.
Which bus transfers the memory address to the IO device or to the memory device?
DMA Direct Memory Access DMA transfers data directly from the drive to memory w/out involving the CPU.
What is logical address space and physical address space?
Logical address is the address generated by the CPU (from the perspective of a program that is running) whereas physical address (or the real address) is the address seen by the memory unit and it allows the data bus to access a particular memory cell in the main memory. All the logical addresses need to be mapped in to physical addresses before they can be used by the MMU. Physical and logical addresses are same when using compile time and load time address binding but they differ when using execution time address binding.
How is data transferred between a CPU and RAM?
A memory management unit (MMU) is a small device between CPU and RAM recalculating the actual memory address, for example to provide an abstraction of virtual memory or other tasks.
Why Is Wait For Memory Function Completed Step Needed When Reading From Or Writing To The Main Memory?
When CPU needs to access a memory location for read or write, it places an address on the address bus. In case of Read, data is meant to be read into Memory Data Register (MDR) and in case of Write, the data (to be written to memory) is put in the MDR.After that CPU issues the Read or Write signal.However, CPU needs to know when the desired memory function (Read or Write) has been completed..This line back to the CPU saying that the operation is complete is sometimes called memory function complete (MFC).In the meanwhile, the instruction or step that is executed by the CPU is known as Wait for Memory Function Completed (WMFC)To summarize:To read (if you are a CPU): Put the desired memory address in the MAR.Assert the Read control line.Wait for the MFC line to be set to 1 by the main memory unit. (Or wait for the appropriate amount of time, if there's no MFC line with your particular main memory unit you are using (rare these days).)Get the data out of the MDR.To write (again, if you are a CPU): Put the desired memory address in the MAR and put the desired data in the MDR.Assert the Write control line.Wait for the MFC line to be set to 1 by the main memory unit
