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almost all modern computers do this (the exceptions are typically simple microcontrollers ). various methods can be used:

  • prefetch
  • pipelining
  • caches
  • etc.
The first computer to do this was the IBM 7030 Stretch transistorized supercomputer introduced in 1961 (it had no integrated circuits at all in it). It used a combination of prefetch, pipelining, and caches to do this.

One computer that I used that implemented prefetch (without pipelining, caches, or other mechanisms) to an extreme was the Delco Magic V implementation of the MIL-STD-1750A architecture. It had a prefetch unit with a FIFO buffer that could store roughly 20 instructions before they were needed by the address evaluation and operand read unit which had another FIFO buffer which could store roughly 20 instructions their operands and the address to store the results to before they were needed by the execution unitwhich had yet another FIFO buffer which could store roughly 20 results and the address to store those results tobefore they were needed by the memory storage unit. In all roughly 60 instructions could be held waiting to be processed between prefetch and storage of results to memory. Multiple levels of scoreboard synchronization logic were used to prevent the prefetch unit and address evaluation and operand read unit from accessing memory or registers pending modification by the memory storage unit or execution unit.

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Q: What processor begins fetching a second instruction before it completes the machine cycle for the first instruction?
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