stack register is a special purpose register.

1.A counter is designed simply by loading an appropriate number into one of the registers and using INR(increment by 1) & DCR(decrement by 1) instructions.
2.A loop is established to update the count,and each count is checked to determine whether it has reached the final number or not.if not then the loop is again repeated.
3.These counters have 1 drawback.i.e.counting is performed at such high speed that only the last count can be observed.to observe counting there must be a proper time delay between counts.

8 bits

There are six classes of interrupt:

*Supervisor Call Interrupts (SVC)

*I/O Interrupts

*External Interrupts

*Restart Interupts

*Program Check Interrupt

*Machine Check Interrupts

The address bus is unidirectional(only in one direction) in the processor. So, the flow of information on this bus is from the microprocessor to the attached device(memory module).

1st address for operand.

2nd address for another operand.

3rd address for store the result.

4th address for next instruction.

If this is a homework assignment, you really should consider doing it yourself

The MVI instruction in the 8085 microprocessor contains 7 or 10 T-Cycles, each one clock cycle, not including wait states. Each cycle starts on the falling edge of CLK.

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T1a - ALE goes high for one half clock. During this time, S0, S1, IO/M-, A15-A8, and AD7-AD0 become valid, and are guaranteed valid at the falling edge of ALE. (AD7-AD0 represent A7-A0, and must be strobed by external hardware.) A15-A0 will be the address of the MVI instruction. Somewhat after ALE, AD7-AD0 will float.

T2a - RD- goes low for one clock cycle. While RD- is low, the external hardware has permission to drive AD7-AD0. It must supply the opcode for MVI. READY is sampled at the beginning of T2 - If it is low, T2 will be repeated, until READY is sampled high.

T3a - RD- remains low for one more half clock cycle. The external hardware must guarantee AD7-AD0 valid by the beginning of T3a. The 8085 samples AD7-AD0 at the beginning of T3a. This will give it the MVI opcode.

T4a - Nothing happens externally. All lines persist their prior state. The 8085 processes the MVI opcode and sets itself up for the required actions.

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T1b - This is the same timing as T1a, except that the address is one greater.

T2b - This is the same timing as T2a. During this time, the external hardware must drive the immediate value of the MVI instruction onto AD7-AD0.

T3b - This is the same timing as T3a. At the conclusion of T3b the 8085 knows the value to store in the destination. If the destination was an internal register, the instruction is complete. If the destination was M, the cycles continue.

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T1c - This is the same timing as T1a, except that the address is the contents of the HL register, H sent on A15-A8, and L sent on AD7-AD0.

T2c - This is the same timing as T1a, except that WR- is used instead of RD-, and the AD7-AD0 lines do not float - they emit the immediate value retrieved in T3b. The AD7-AD0 line will change sometime between ALE and WR-.

T3c - This is the same timing as T3a, except that WR- goes high at the beginning instead of at the halfway point. The external hardware is expected to save the AD7-AD0 lines into the address specified during T1c on the rising edge of WR-. The 8085 will persist the AD7-AD0 lines for one half clock cycle to guarantee the AD7-AD0 lines.

According to Win Ballada ,CPA, MBA that the repetitious procedure can be avoided with the introduction of an alternative device called cash priority program. this program which is prepared at the start of the liquidation processwill help the partner's project when they can expert to be included in the cash distribution.

when interrupts requests arrive from two or more devices simultaneously , the process has to decide which request should be serviced first and which one should delayed. the processor takes the decision with the help of interrupt priorities.

RET pops the PC off of the stack, while IRET pops both the flags and the PC off of the stack.

what is a internal bus

An accession register is a record of all items that have been added to a collection. This can include items that have been donated, purchased, or found. The accession register can be used to track the growth of a collection over time, and to ensure that all items in the collection are accounted for. The register can also be used to help plan future acquisitions, and to track the provenance of items in the collection.

we use LDA ## where ## is an 8 bit hexadecimal data

15

Early microprocessor neded clock input to be given externally, i.e. an extra clock generator chip is necessary. the clock generator chip had two pins between which a crstal or an RC circuit could be connected for the generation of basic frequency desired. however, microprocessor, that were designed after 1978(Intel 8085, M6809, etc.) had the clock generator circuit embedded in the microprocesor chip.

The number of lines on a bus that can hold data, for example, 8, 16, 32, and 64 lines, which can accommodate 8, 16, 32, and 64 bits at a time.

It encounters the HLT instruction when there is not an endless loop or other things that are done endlessly.

1) Fetch is the first of two stages involved in computer processing. The processor operates by processing instructions in what is called the "fetch/execute cycle." The processor fetches (reads from memory) an instruction and then, depending on the instruction, executes it (takes some further action with it, such as shifting bits to the right or left). Then it fetches the next instruction, and so forth.

there is an a