MVI C,01h
MVI E,01h
MVI A,09h
LABEL:
SBB C
JZ LABEL1
INR C
INR C
INR E
JMP LABEL
LABEL1:MOV A,E
HLT
jus change the value of A in the 3rd line according to whtever number u wish to square rrot..haffun!
i don't know because i cant find it do they even make em' ask your self that though cuz i don't either?
The emitter of a transistor was placed a micrometer distance between two, so it was called a microprocessor. Technology advanced, and the distance was improved to nano meter. Still, they call it micro.
Computers are so quick they transfer 1GB at 2 seconds an hour
The processor has 5 interrupts. They are presented below in the order of their priority (from lowest to highest):
INTR is maskable 8080A compatible interrupt. When the interrupt occurs the processor fetches from the bus one instruction, usually one of these instructions:
RST5.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 002Ch (hexadecimal) address.
RST6.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 0034h (hexadecimal) address.
RST7.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 003Ch (hexadecimal) address.
Trap is a non-maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 0024h (hexadecimal) address.
All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5, RST6.5 and RST7.5 interrupts can be enabled or disabled individually using SIM instruction.
Direct addressing mode means the operand address is contained in the instruction. In the 8085, an example is LDA 1234H, which loads the accumulator with the contents of memory location 1234H. In the 8086/8088, an example is MOV AL,[1234H], which accomplishes nearly the same thing.
Indirect addressing mode means the operand address is contained in a register. In the 8085, an example is LDAX B, which loads the accumulator with the contents of the memory location specified in register BC. In the 8086/8088, an example is MOV AL,[BX], which accomplishes nearly the same thing.
32 bit address line can access 4GB of memory. As 2^10 -> 1KB; 2^20 -> 2MB; 2^30 -> 1GB and so on.... 32 bit gives (2^30) * (2^2) = 1GB * 4 = 4GB;
ALE, or Address Latch Enable, tells hardware logic that the data on the data bus represents address information that should be latched. This is a technique used called multiplexing, and it allows for the pin count on the processor chip to be reduced.
It works on 8 bit
lower address lines has to be multiplexed with data lines
Appropriate control signals have to be generated to interface with memory and I/O devices
8 bit processors are slow
Memory is just 64 kb
By Anmol Bhardwaj
SUSCET Tangori Mohali ( India)
we can do this using two techniques:
here i m assuming that two number which is to be multiplied are given..
say 05H and 04H,
so coz 5*4 = 5+5+5+5 = 20
and 4*5 = 4+4+4+4+4 = 20
use this concept ...
MVI A,05H;
MVI B,04H;
L1:
ADD A;
DCR B;
JNZ : L1;
STA 2004H;
HLTType your answer here...
The 8086 has a 20 bit address bus and a 16 bit data bus. The low order 16 bits of the address bus share the same 16 pins as the data bus. The low order 16 bits of the address are emitted in the first clock cycle of a memory access cycle. External logic is expected to latch that address. Then the bus becomes a data bus. The high order 4 bits of the address bus are handled separately.
The determination of operand size (8 bit vs 16 bit) is made by BHE and A0. If BHE is high, it is a 16 bit operand at an even address. If BHE is low and A0 is low, it is an 8 bit operand at an even address. If BHE is low and A0 is high, it is an 8 bit operand at an odd address.
The NOP instruction is a no-operation instruction. It does nothing to the state of the machine, except to use some time. In the case of the 8085, it uses four clock cycles plus however many wait states are need to access the NOP instruction from memory.
A microprocessor that uses 24 bit addressing, such as the Intel 80286, can address 224 or 16,777,216 memory locations. The IBM MainFrame, 360/44 or any modern version running in AMODE=24 also has the same capacity.
Because its rude. Communication is a street where both cars are trying to pass at the same time, one has to give way so the other can pass
The clock speed of the 8085 depends on the particular chip chosen. The basic 8085 could run up to around 3 MHz. The -1 version could run up to around 6 MHz. The -2 version could run up to around 5 MHz.
In each case, the crystal frequency had to be exactly twice the desired clock frequency, i.e. 6 Mhz, 12 MHz, and 10 MHz, respectively.
In all cases, the minimum clock frequency was 500 KHz. (Crystal 1 MHz)
Address Latch Enable:-
Address Latch was Intel's way of limiting the number of pins on their early microprocessors, to limit the production cost.
Sadly this "feature" remained in Intel processor architecture for several generations, despite the fact that production cost was no longer an issue.
What it does: On the early processors there was an 8 bit bus acting both as an address and a data bus (to save pins). Then there was the ALE (Address Latch Enable) pin, that determined if the bus should act as data or address bus. This of course decreased the efficiency of the processor, because you had to switch back and forth between the two states, according to which bus was needed.
You need 20 bits of address bus to address 1 Mb of memory.
The SHLD instruction in the 8085 requires 6 (opcode, decode, and increment) + 3 (low address fetch) + 3 (high address fetch) + 3 (low, L, store) + 3 (high, H, store) cycles which equals 18 cycles, not including wait states.
in Intel core 2 duo address bus is 32 and data bus is also 32 see it in file:///C:/Users/chethan/Downloads/Today's%20Hotness%20%20The%20Core%202%20Duo%20%20%20Intel's%2015%20Most%20Unforgettable%20x86%20CPUs.htm
the 8085 microprocessor is a 8-bit microprocessor and these are bidirectional but the address lines are unidirectional.these address lines are used to address the location of the instruction in memory .these data lines are used to transfer data between processor and peripheral devices. when the address of the instruction will be recognized by the address lines the data will be send to the processor
therefore the 16 address lines are not act as a data lines in 8085
Ted hughes was the first person who designed microprocessors.
In 1971 Ted hughes make first microprocessor for intel.
The name of the first microprocessor was:
Intel-4004.
It contains lacs of electronic circuits.
It means speaking to someone directly. Susan, clean up your room. Bob, hand me a flashlight. I told you already, Mom, I am not going. In these sentences, the direct address is to Susan, Bob, and Mom.
Instruction register is use to store the next instruction to be executed.
Instruction decoder is use to decode the instruction come from the memory and tell the CPU what is instruction really are. (CPU interpret instruction is different from the data store in the memory . A good example is , memory can store hexadecimal, but device only can read binary data.) without decoder the device cannot indicate or recognize the data )
Distinction
"memory can store hexadecimal, but device only can read binary data" This is an improperly worded, misleading statement. The difference between binary and hexadecimal is purely interpretive. Reading hexadecimal is a function of dividing the bits into groups of 4 and assigning a unique symbol to the pattern; 0-9 + A-F. This is only translating from one numbering system to another. The memory isn't specifically able to store hexadecimal as opposed to binary; it stores a BYTE as a group of EIGHT BITS no matter what. So even if the hardware is designed to move 64 bits at a time, grouping the bits into nibbles of four bits is how we interpret the bit pattern in hexadecimal.
Another Answer <<< Truth!
Instruction Register is where the instruction bit pattern is loaded for execution. Instruction Decoder is all the hardware logic that is cascade triggered by the instruction bit pattern during execution.