basic gates like XOR already exist in VHDL.
Below code can implement NAND gate in VHDL. The code is written in behavioral model. Library ieee; use ieee.std_logic_1164.all; Entity gates is port (a,b : in std_logic; c : out std_logic); end gates ; architecture and1 of gates is begin process(a,b) Begin If (a=1 and b=1) then C<='0'; Else C<= '1'; End if; End process; End and1;
Below code can implement NAND gate in VHDL. The code is written in data flow model. Library ieee; use ieee.std_logic_1164.all; Entity gates is port (a,b : in std_logic; c : out std_logic); end gates ; architecture and1 of gates is begin c<=a nand b; end and1;
Below code can implement NOT gate in VHDL. The code is written in data flow model. Library ieee; use ieee.std_logic_1164.all; Entity gates is port (a : in std_logic; c : out std_logic); end gates ; architecture and1 of gates is begin c<=not a; end and1;
Below code can implement AND gate in VHDL. The code is written in data flow model. Library ieee; use ieee.std_logic_1164.all; Entity gates is port (a,b : in std_logic; c : out std_logic); end gates ; architecture and1 of gates is begin c<=a and b; end and1;
Below code can implement OR gate in VHDL. The code is written in behavioral model. Library ieee; use ieee.std_logic_1164.all; Entity gates is port (a,b : in std_logic; c : out std_logic); end gates ; architecture and1 of gates is begin process(a,b) Begin If (a=1 or b=1) then C<='1'; Else C<= '0'; End if; End process; End and1;
They are very much the same, except VHDL syntax is derived from Ada while Verilog syntax is derived from C. ==================================== moreover, VHDL is a system level language whereas verilog is a gate level (circuit level) language. Hence, verilog is easy to learn than VHDL.
In the synthesis part of a VHDL code, the EDA tool provides technology schematic. It describes the structure and sub-structures of the design. We can watch our design from the system level to the gate level.
AND gate, INVERTER gate and OR gate. Hope this would help.
Since a fulladder can be obtained by using 2 halfadders & 1 OR gate.....so we have to call an halfadder program as well as an OR program......this can be implemented easily with the help of structural model rather than dataflow and behavoioural model
VHDL is the VHSIC Hardware Description Language. VHSIC is an abbreviation for Very High Speed Integrated Circuit. It can describe the behaviour and structure of electronic systems, but is particularly suited as a language to describe the structure and behaviour of digital electronic hardware designs, such as ASICs and FPGAs as well as conventional digital circuits. VHDL is an international standard, regulated by the IEEE. Simulation and synthesis are the two main kinds of tools which operate on the VHDL language. VHDL allows designs to be described using any methodology - top down, bottom up or middle out! VHDL can be used to describe hardware at the gate level or in a more abstract way.
A logic gate is used to implement any digital logic. It may be AND, OR, XOR, NOT, XNOR, NAND, NOR. These logic gates can be used to implement the output equations of digital circuits in order to design them.
VHDL is basically a hardware description language. To describe hardware as a program that can be dumped into a PLD, we use VHDL. It is essential to represent hardware as program so that it can be tested before realizing it physically. If there are any errors, they can be corrected here itself.