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Below code can implement AND gate in VHDL. The code is written in data flow model.
Library ieee;
use ieee.std_logic_1164.all;
Entity gates is
port (a,b : in std_logic; c : out std_logic);
end gates ;
architecture and1 of gates is
begin
c<=a and b;
end and1;
Wiki User
∙ 11y ago
Wiki User
∙ 11y agoBelow code can implement OR gate in VHDL. The code is written in data flow model.
Library ieee;
use ieee.std_logic_1164.all;
Entity gates is
port (a,b : in std_logic; c : out std_logic);
end gates ;
architecture and1 of gates is
begin
c<=a or b;
end and1;
Wiki User
∙ 11y agoBelow code can implement XOR gate in VHDL. The code is written in data flow model.
Library ieee;
use ieee.std_logic_1164.all;
Entity gates is
port (a,b : in std_logic; c : out std_logic);
end gates ;
architecture and1 of gates is
begin
c<=a xor b;
end and1;
Wiki User
∙ 11y ago%Below code can implement AND gate in VHDL.
%The code is written in behavioral model.
Library ieee;
use ieee.std_logic_1164.all;
Entity gates is
port (a,b
: in std_logic;
c : out std_logic);
end gates ;
Architecture behavioural of gates is
begin
process(a,b)
begin
If (a='1' and b='1') then
c<='1';
else
c<=
'0';
end if;
end process;
end behavioural;
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