0
Intel 8086 and 8088
The Intel 8086/8088 family of microprocessors is a 16 bit architecture on a 16 bit (8086) or an 8 bit (8088) bus. The 8088 was the processor in the original IBM PC, and has evolved into the most popular processor used today in PC's and servers.
1,056 Questions
What is the difference between a physical address and a mailing address?
Real memory uses Physical addresses.These are the members that the memory chips react to on the bus. Virtual addresses are the logical addresses that nrefer to a process' address space. Thus, a machine with a 16-bit word can generate virtual addresses upto 64K, regardless of whether the machine has more or less memory than 64 KB
How wide can the external data bus be?
The external data bus can be as wide as desired, given the necessary compromises between performance, complexity, and cost. The wider the bus, the faster the theoretical aggregate data transfer rate.
In the 8085 and 8088, the external data bus is 8 bits wide; in the 8086, it is 16 bits wide; in the 80386, it is 32 bits wide; and in the modern incarnations of 64 bit processors, it is 64 bits wide.
How many nuMBer of address lines required for 1 MB memory?
Firstly we need to convert Mb's into bits
i.e 1Mb=1024x1024
= 210x210
=220
That means there are 220 memory locations and we will need 20 address lines.
Explain stack structure of 8086?
The stack in the 8086/8088 microprocessor, like that in many microprocessors, is a region of memory that can store information for later retrieval. It is called a stack, because you "stack" things on it. The philosophy is that you retrieve (pop) things in the opposite order of storing (push) them. In the 8086/8088, the stack pointer is SS:SP, which is a 16 bit pointer into a 20 bit address space. It, at any point of time, points to the last item pushed on the stack. If the stack is empty, it points to the highest address of the stack plus one. In a push operation, the SP register is decremented by two, and the data to be pushed is stored at that address, low order byte first. In a pop operation, the data to be popped is retrieved from that address, again low order byte first, and then the SP register is incremented by two. Some instructions, such as a FAR CALL, or FAR RETURN push or pop more than two bytes on the stack. It is also possible to allocate temporary storage on the stack. You simply decrement the SP register by some amount, use that memory, and then increment the SP register to release the memory. This is known as a stack frame. In fact, the BP register makes is very easy to do so. You use BP to separate arguments from local data - arguments will be above BP, and local data will be below BP. Memory reference instructions that are relative to BP, i.e. [BP+6] or [BP-48] will automatically use the SS segment register.
What is an instruction queue in 8086?
The 8086/8088 instruction queue is a buffer that holds opcode bytes that have been prefetched by the bus interface unit. This speed up operations of the processor by helping to reduce fetches latency, i.e. to improve the probability that an opcode byte fetched by the processor is already available.
This works best when there is no branching, as a branch would invalidate the queue. Advanced processors attempt to "predict" the branch, making the probability even better.
Explain different types of addressing mode?
Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how machine language instructions in that architecture identify the operand (or operands) of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.
Number of addressing modesDifferent computer architectures vary greatly as to the number of addressing modes they provide in hardware. There are some benefits to eliminating complex addressing modes and using only one or a few simpler addressing modes, even though it requires a few extra instructions, and perhaps an extra register.[1] It has proven[citation needed] much easier to design pipelined CPUs if the only addressing modes available are simple ones.Most RISC machines have only about five simple addressing modes, while CISC machines such as the DEC VAX supermini have over a dozen addressing modes, some of which are quite complicated. The IBMSystem/360 mainframe had only three addressing modes; a few more have been added for the System/390.
When there are only a few addressing modes, the particular addressing mode required is usually encoded within the instruction code (e.g. IBM System/390, most RISC). But when there are lots of addressing modes, a specific field is often set aside in the instruction to specify the addressing mode. The DEC VAX allowed multiple memory operands for almost all instructions, and so reserved the first few bits of each operand specifier to indicate the addressing mode for that particular operand. Keeping the addressing mode specifier bits separate from the opcode operation bits produces an orthogonal instruction set.
Even on a computer with many addressing modes, measurements of actual programs[citation needed] indicate that the simple addressing modes listed below account for some 90% or more of all addressing modes used. Since most such measurements are based on code generated from high-level languages by compilers, this reflects to some extent the limitations of the compilers being used
What is microprocessor and explain the parts of microprocessor using block diagram?
A microprocessor is an integrated circuit that serves as the central processing unit (CPU) of a computer. It executes instructions and performs arithmetic and logic operations. The main parts of a microprocessor include the arithmetic logic unit (ALU) for mathematical calculations, the control unit for instruction interpretation and sequencing, registers for temporary data storage, and buses for data and address transmission. These components work together to process data and execute instructions in a computer system.
18 address lines is how much memory?
to find the memory from address lines. you just have to make address liness power of 2, as shown below for 12 address lines 212 bits. 212 = 22 * 210 = 4 Kb
that means we can address 4 Kb from 12 address lines.........
Diffrentiate between minimum mode and maximum modes in 8086 processors?
1:in min mode mn/mx- is connected to vcc .here now mn will be one AND IN MIN MODE ONLY ONE PROCESSOR IS PRESENT WITHOUT ANY CO PROCESSOR . 2: in max mode mn/mx- is cnnected to ground now the mx will become 1. AND IN MAX MODE MANY PROCESSORS ARE CONNECTED TO EACH OTHER WITHOUT ANY CO PROCESSOR EX FOR COPROCESSOR IS 8284
1:in min mode mn/mx- is connected to vcc .here now mn will be one AND IN MIN MODE ONLY ONE PROCESSOR IS PRESENT WITHOUT ANY CO PROCESSOR . 2: in max mode mn/mx- is cnnected to ground now the mx will become 1. AND IN MAX MODE MANY PROCESSORS ARE CONNECTED TO EACH OTHER WITHOUT ANY CO PROCESSOR EX FOR COPROCESSOR IS 8284
One code-segment. One data-segment. Thus neither code nor data may be greater than 64K
Implementation of binary search algorithm using ASM assembler in 8086?
Hi, I hope this is useful
http://www.indiastudychannel.com/projects/2748-Assembly-language-program-for-Binary-search.aspx
good luck!
What is the fastest laptop processor readily available today?
EDIT:
After all that nonsence... AS of 2012 um... july 25
For the alienware m18x....
3rd Generation Intel® Core™ i7-3920XM (8MB Cache, up to 4.1GHz Overclocked*)
That would burn the whole battery in 1 hr so better have a desktop intead...
It would also cost 1.5k so better have the desktop....
Which type of bridge would be used to connect an ethernet segment with a token ring segment?
You will need a router. Token Ring and Ethernet refer to two different layer two protocols. You will need a layer three device to encapsulate the data for communication between the two networks. A bridge refers to a layer two device.
What is the register of a microprocessor?
CPU's may have several types of registers and different manufacturers can throw in whatever they want. Typically there will be general purpose registers in varying numbers, depending on the manufacturer, program counter registers which contain the address of the next instruction to be executed, there may be stack pointer registers and whatever else the engineer(s) imagined.
It depends on the CPU used.
The 80x86 Processor can be broken into 4 categories...
- General Purpose Registers
- Special purpose Accessible Application registers
- Segement Registers
- Special Kernel Mode Registers
EAX, EBX, ECX, EDX, ESI, EBP.
AX, BX, CX, DX, SI, DI, BP, and SP
AL, AH, BL, BH, CL, CH, DL, and DH
- A processor often contains several kinds of registers, that can be classified according to their content or instructions that operate on them:
User-accessible Registers - The most common division of user-accessible registers is into data registers and address registers.
Data registers are used to hold numeric values such as integer and floating-point values. In some older and low end CPUs, a special data register, known as the accumulator, is used implicitly for many operations.
Address registers hold addresses and are used by instructions that indirectly access memory.
Some processors contain registers that may only be used to hold an address or only to hold numeric values (in some cases used as an index register whose value is added as an offset from some address); others allow registers to hold either kind of quantity. A wide variety of possible addressing modes, used to specify the effective address of an operand, exist.
A stack pointer, sometimes called a stack register, is the name given to a register that can be used by some instructions to maintain a stack (data structure).
Conditional registers hold truth values often used to determine whether some instruction should or should not be executed.
General purpose registers (GPRs) can store both data and addresses, i.e., they are combined Data/Address registers.
Floating point registers (FPRs) store floating point numbers in many architectures.
Constant registers hold read-only values such as zero, one, or pi.
CPU's may have several types of registers and different manufacturers can throw in whatever they want. Typically there will be general purpose registers in varying numbers, depending on the manufacturer, program counter registers which contain the address of the next instruction to be executed, there may be stack pointer registers and whatever else the engineer(s) imagined.
It depends on the CPU used.
The 80x86 Processor can be broken into 4 categories...
- General Purpose Registers
- Special purpose Accessible Application registers
- Segement Registers
- Special Kernel Mode Registers
EAX, EBX, ECX, EDX, ESI, EBP.
AX, BX, CX, DX, SI, DI, BP, and SP
AL, AH, BL, BH, CL, CH, DL, and DH
How many memory locations address bus can access?
A 10 bit address bus can address 210, or 1024 different locations.
What determines whether a microprocessor is considered an 8-bit a 16-bit or a 32-bit device?
The number of bits a CPU uses to represent integer numbers (as opposed to floating point numbers or memory addresses) is often called "register width", "word size", "bit width", "data path width", or "integer precision".
This number is often considered one of the most important characteristics of a CPU.
Most CPUs are 8 bit CPUs. An 8 bit CPU -- i.e., a CPU where each register holds 8 bits -- typically has a 8 bit data bus and a 16 bit address bus.
One of the first 32 bit CPUs -- the MC68008 -- had registers that held 32 bits, a 20 bit address bus, and an 8 bit data bus.
Some popular 32 bit CPUs -- i.e., CPUs with registers that hold 32 bits -- had a 32 bit data bus and a 24 bit address bus.
Explain the real mode in 8086?
Real mode is a term that was introduced for the 80286 and higher processors. It represents the default (power on) mode of an 80286 or higher processor, as opposed to one of the various protected modes. Real mode does not apply specifically to the 8086/8088. In the 80286 and above, real mode operates very much like the 8086/8088.
What is the size of each memory segment of 8086 is?
The 8086 was only capable of addressing 1Mbyte of memory. It was divided into segments of 65536 bytes (64 KB) each meaning about 16 segments.
How many address bits are required for accessing 1GB RAM?
It requires 30 address bits to address 1GB of RAM.
230 = 1,073,741,824
Real time applications of 8085 microprocessor?
AIRCRAFT MICROPROCESSOR CONTROL - 1CV
(009826)
Area /Catalog # : AERO / 2012
General Information, Semester 1, 2008
Course Coordinator: Dr Bruce Wedding
Office: F2-50 Phone: 8302-3052 (VoiceMail)
Prerequisites
AERO 1012 Aviation Physics 2N is a prerequisite for this course. Students who have not passed both 1
st
year general
physics courses are advised to un-enroll from this course and consult their program director for advice on an
appropriate academic pathway through their program.
Aim
To introduce the student to basic electronics, microprocessors and control systems in order to advance an understanding
of their application to aviation ie. 'glass cockpit' systems
Objectives
On completion of this course, the student should be able to:
* demonstrate a sound knowledge of microprocessor basics, control theory, physical transducers and their
application in aviation.
* undertake experiments in basic electronics and transducers followed by a series of computer based control
strategies.
Syllabus
Microcomputer organisation; execution of instructions; microprocessor architecture; logic; introduction to
microprocessor applications; transducers; control theory; aircraft control examples; analog & electronic aircraft
instrumentation examples; high level language micro controllers; communication between systems.
Reference books
There will be no single text book for this course which completely covers all the material however the principle
reference book will be
Burton M, Electronics, Logic and Auto-Flight Instruments, Airlife, 1997 [ 629.13252 B973 - 3 day reserve ]
I list a selection of other reference books which are available in either the library ( look under 629.X), the campus book
shop, or the Pilot's Shop at Parafield airport.
Johnson CD, Microprocessor Based Process Control, Prentice-Hall, 1984 [ 629.895 J66 - 3 day ]
Collinson RPG, Introduction to Avionics Systems, 2
nd
Ed, Kluwer Academic Pub., 2003
Siuru B & Busick JD, Future Flight - the next generation of aircraft technology, TAB AERO McGraw-Hill
[ 629.13334 S623.2 ]
McCormick BW, Aerodynamics, Aeronautics and Flight Mechanics, 2
nd
Ed, John Wiley & Sons, 1995
[ 629.1323 M131.2 - 3 day ]
Assessment
Continuous assessment 25%
Practical 25%
Examination (1 x 2 hr.) 50%
The continuous assessment will consist of quizzes and problem papers delivered as
per the schedule below. The quizzes (approx 20 minutes) will evaluate the students
conceptual knowledge as well as small problem solving skills. The problem papers
will each consist of 3 or 4 numerically based problems.
The relative weighting of quizzes and problem papers will be:
Quizzes (Formative) 0% Tests (3 x 9%) 25% Dr A Bruce Wedding D:\A_Teaching\DOCS\Subject Outlines\AMC 1CV_Outline 2008.doc 13/05/2008
Program
There will be 2 hours of lectures per week, with tutorials in the odd numbered teaching weeks ie. week 3, 5, 7 etc. and
the Practical will begin in week 3. Students will attend only one 2 hour practical sessions each week. Room details are;
Lectures Monday 1-3 pm D1-05
Tutorials Thursday 1 pm P2-28
Practical s Mon 3-5 pm Thur 2-4 pm Fri 2-4 pm F2-04A
Schedule
The following represents the proposed schedule (framework) of studies for semester 1.
Week Monday Lectures Thursday Tutorial Practicals
1 Free Free
2 Holiday Monday Free
3 Sample problems Prac #1
4 Holiday Monday Lecture + Quiz 0 One out, all out
5 Quiz 1, TutorialVideo Prac #2
6 Test #1 Prac #3
MID SEMESTER BREAK
MID SEMESTER BREAK
7 Feedback Tutorial Prac #4
8 Prac #5
9 Quiz 2, Tutorial Video Prac #6
10 Test #2 Prac #7
11 Feedback Tutorial Prac #8
12 Inc. Exam Preparation Quiz 3 Prac #9
13 Holiday Monday Test #3 Free
SVac Quiz & Test Feedback Free
Examinations
The examination will be of 2 hours duration and will be held in the official examination period at the end of the
semester at a date to be advised. The exam covers all work from the lectures (as per the syllabus), the practical sessions
and tutorials during the semester.
A deferred examination may be granted if a student is unable to sit for an examination because of illness. An
application for a deferred examination must be accompanied by a doctors certificate and must be lodged with your
division office within seven days of the examination.
Plagiarism
Please note that the University has a policy on plagiarism. Plagiarism is the copying of work or data of other people
without giving them due acknowledgment. This includes word-for-word copying of sentences or whole paragraphs
from books, articles, etc, without clearly indicating where you got the material from. It also includes using very close
paraphrasing of sentences or paragraphs without due acknowledgment.
Deliberate plagiarism is regarded as a serious form of academic misconduct and offenders (both the person copying and
the person knowingly supplying the information) are liable to be penalized by a fail for the particular assignment or the
entire course. Repeated plagiarism may result in your expulsion from the University.
For a more complete definition of plagiarism refer to the section on Academic Misconduct in the University Calendar
or for definitions of plagiarism, educative process, penalties and of the procedures which will be followed in a case of
suspected plagiarism see the University Web page www.unisa.edu.au/adminfo/policies/manual/index.htm Section 5 Academic Misconduct, 5.1.2 Plagiarism.erterter
Why tri-state device is useful in bus oriented system?
In a multiplexed bus system, many devices are connected to
a common bus. If 2 or more devices attempt to use the bus
at the same time , then data will be lost. Thus only one
one device must be allowed to use the bus at a time. One
method is to connect the devices through tri-state
devices , which when disabled will effectively disconnect
devices from the bus.
How many bits is the data bus for a 486dx4 processor?
A 386SX processor has 16-bits and 386DX has 32-bits
How many addressing mode of 8086 assembly language program?
there are five addressing modes in 8086
they are :
1->direct addressing
2->Indirect addressing
3->index addressing
4->immediate addressing
5->register addressing
