Intel 8085

AIRCRAFT MICROPROCESSOR CONTROL - 1CV

(009826)

Area /Catalog # : AERO / 2012

General Information, Semester 1, 2008

Course Coordinator: Dr Bruce Wedding

Office: F2-50 Phone: 8302-3052 (VoiceMail)

Prerequisites

AERO 1012 Aviation Physics 2N is a prerequisite for this course. Students who have not passed both 1

st

year general

physics courses are advised to un-enroll from this course and consult their program director for advice on an

appropriate academic pathway through their program.

Aim

To introduce the student to basic electronics, microprocessors and control systems in order to advance an understanding

of their application to aviation ie. 'glass cockpit' systems

Objectives

On completion of this course, the student should be able to:

* demonstrate a sound knowledge of microprocessor basics, control theory, physical transducers and their

application in aviation.

* undertake experiments in basic electronics and transducers followed by a series of computer based control

strategies.

Syllabus

Microcomputer organisation; execution of instructions; microprocessor architecture; logic; introduction to

microprocessor applications; transducers; control theory; aircraft control examples; analog & electronic aircraft

instrumentation examples; high level language micro controllers; communication between systems.

Reference books

There will be no single text book for this course which completely covers all the material however the principle

reference book will be

Burton M, Electronics, Logic and Auto-Flight Instruments, Airlife, 1997 [ 629.13252 B973 - 3 day reserve ]

I list a selection of other reference books which are available in either the library ( look under 629.X), the campus book

shop, or the Pilot's Shop at Parafield airport.

Johnson CD, Microprocessor Based Process Control, Prentice-Hall, 1984 [ 629.895 J66 - 3 day ]

Collinson RPG, Introduction to Avionics Systems, 2

nd

Ed, Kluwer Academic Pub., 2003

Siuru B & Busick JD, Future Flight - the next generation of aircraft technology, TAB AERO McGraw-Hill

[ 629.13334 S623.2 ]

McCormick BW, Aerodynamics, Aeronautics and Flight Mechanics, 2

nd

Ed, John Wiley & Sons, 1995

[ 629.1323 M131.2 - 3 day ]

Assessment

Continuous assessment 25%

Practical 25%

Examination (1 x 2 hr.) 50%

The continuous assessment will consist of quizzes and problem papers delivered as

per the schedule below. The quizzes (approx 20 minutes) will evaluate the students

conceptual knowledge as well as small problem solving skills. The problem papers

will each consist of 3 or 4 numerically based problems.

The relative weighting of quizzes and problem papers will be:

Quizzes (Formative) 0% Tests (3 x 9%) 25% Dr A Bruce Wedding D:\A_Teaching\DOCS\Subject Outlines\AMC 1CV_Outline 2008.doc 13/05/2008

Program

There will be 2 hours of lectures per week, with tutorials in the odd numbered teaching weeks ie. week 3, 5, 7 etc. and

the Practical will begin in week 3. Students will attend only one 2 hour practical sessions each week. Room details are;

Lectures Monday 1-3 pm D1-05

Tutorials Thursday 1 pm P2-28

Practical s Mon 3-5 pm Thur 2-4 pm Fri 2-4 pm F2-04A

Schedule

The following represents the proposed schedule (framework) of studies for semester 1.

Week Monday Lectures Thursday Tutorial Practicals

1 Free Free

2 Holiday Monday Free

3 Sample problems Prac #1

4 Holiday Monday Lecture + Quiz 0 One out, all out

5 Quiz 1, TutorialVideo Prac #2

6 Test #1 Prac #3

MID SEMESTER BREAK

MID SEMESTER BREAK

7 Feedback Tutorial Prac #4

8 Prac #5

9 Quiz 2, Tutorial Video Prac #6

10 Test #2 Prac #7

11 Feedback Tutorial Prac #8

12 Inc. Exam Preparation Quiz 3 Prac #9

13 Holiday Monday Test #3 Free

SVac Quiz & Test Feedback Free

Examinations

The examination will be of 2 hours duration and will be held in the official examination period at the end of the

semester at a date to be advised. The exam covers all work from the lectures (as per the syllabus), the practical sessions

and tutorials during the semester.

A deferred examination may be granted if a student is unable to sit for an examination because of illness. An

application for a deferred examination must be accompanied by a doctors certificate and must be lodged with your

division office within seven days of the examination.

Plagiarism

Please note that the University has a policy on plagiarism. Plagiarism is the copying of work or data of other people

without giving them due acknowledgment. This includes word-for-word copying of sentences or whole paragraphs

from books, articles, etc, without clearly indicating where you got the material from. It also includes using very close

paraphrasing of sentences or paragraphs without due acknowledgment.

Deliberate plagiarism is regarded as a serious form of academic misconduct and offenders (both the person copying and

the person knowingly supplying the information) are liable to be penalized by a fail for the particular assignment or the

entire course. Repeated plagiarism may result in your expulsion from the University.

For a more complete definition of plagiarism refer to the section on Academic Misconduct in the University Calendar

or for definitions of plagiarism, educative process, penalties and of the procedures which will be followed in a case of

suspected plagiarism see the University Web page www.unisa.edu.au/adminfo/policies/manual/index.htm Section 5 Academic Misconduct, 5.1.2 Plagiarism.erterter

a. tell about something in the past.

A 386SX processor has 16-bits and 386DX has 32-bits

no, i discovered today

program counter holds the address of the next instruction.

b/c the 8085 microprocessor is the first 8 bit microprocessor which Intel is produces in 1877 and this is the first general purpose 8 bit microprocessor.

there was an 8 bit general purpose register before 8085 named as 8008 but this microprocessor is not functional 8 bit microprocessor

how many interrupts in 8051

Flags are used to indicate the status of various things, usually following some kind of operation. For instance, the ZERO flag indicates the result is zero, the CARRY flag indicates the operation results in a carry, the NEGATIVE flag indicates the result is negative, etc.

Flags can be used in loop control. For instance you can decrement a counter at the end of a loop, and jump conditionally to the top of the loop if the counter is non zero.

ACI n |CE|*****| 7|Add with Carry Immediate |A=A+n+CY |

|ADC r |8F|*****| 4|Add with Carry |A=A+r+CY(21X)|

|ADC M |8E|*****| 7|Add with Carry to Memory |A=A+[HL]+CY |

|ADD r |87|*****| 4|Add |A=A+r (20X)|

|ADD M |86|*****| 7|Add to Memory |A=A+[HL] |

|ADI n |C6|*****| 7|Add Immediate |A=A+n |

|ANA r |A7|****0| 4|AND Accumulator |A=A&r (24X)|

|ANA M |A6|****0| 7|AND Accumulator and Memory|A=A&[HL] |

|ANI n |E6|**0*0| 7|AND Immediate |A=A&n |

|CALL a |CD|-----|18|Call unconditional |-[SP]=PC,PC=a|

|CC a |DC|-----| 9|Call on Carry |If CY=1(18~s)|

|CM a |FC|-----| 9|Call on Minus |If S=1 (18~s)|

|CMA |2F|-----| 4|Complement Accumulator |A=~A |

|CMC |3F|----*| 4|Complement Carry |CY=~CY |

|CMP r |BF|*****| 4|Compare |A-r (27X)|

|CMP M |BF|*****| 7|Compare with Memory |A-[HL] |

|CNC a |D4|-----| 9|Call on No Carry |If CY=0(18~s)|

|CNZ a |C4|-----| 9|Call on No Zero |If Z=0 (18~s)|

|CP a |F4|-----| 9|Call on Plus |If S=0 (18~s)|

|CPE a |EC|-----| 9|Call on Parity Even |If P=1 (18~s)|

|CPI n |FE|*****| 7|Compare Immediate |A-n |

|CPO a |E4|-----| 9|Call on Parity Odd |If P=0 (18~s)|

|CZ a |CC|-----| 9|Call on Zero |If Z=1 (18~s)|

|DAA |27|*****| 4|Decimal Adjust Accumulator|A=BCD format |

|DAD B |09|----*|10|Double Add BC to HL |HL=HL+BC |

|DAD D |19|----*|10|Double Add DE to HL |HL=HL+DE |

|DAD H |29|----*|10|Double Add HL to HL |HL=HL+HL |

|DAD SP |39|----*|10|Double Add SP to HL |HL=HL+SP |

|DCR r |3D|****-| 4|Decrement |r=r-1 (0X5)|

|DCR M |35|****-|10|Decrement Memory |[HL]=[HL]-1 |

|DCX B |0B|-----| 6|Decrement BC |BC=BC-1 |

|DCX D |1B|-----| 6|Decrement DE |DE=DE-1 |

|DCX H |2B|-----| 6|Decrement HL |HL=HL-1 |

|DCX SP |3B|-----| 6|Decrement Stack Pointer |SP=SP-1 |

|DI |F3|-----| 4|Disable Interrupts | |

|EI |FB|-----| 4|Enable Interrupts | |

|HLT |76|-----| 5|Halt | |

|IN p |DB|-----|10|Input |A=[p] |

|INR r |3C|****-| 4|Increment |r=r+1 (0X4)|

|INR M |3C|****-|10|Increment Memory |[HL]=[HL]+1 |

|INX B |03|-----| 6|Increment BC |BC=BC+1 |

|INX D |13|-----| 6|Increment DE |DE=DE+1 |

|INX H |23|-----| 6|Increment HL |HL=HL+1 |

|INX SP |33|-----| 6|Increment Stack Pointer |SP=SP+1 |

|JMP a |C3|-----| 7|Jump unconditional |PC=a |

|JC a |DA|-----| 7|Jump on Carry |If CY=1(10~s)|

|JM a |FA|-----| 7|Jump on Minus |If S=1 (10~s)|

|JNC a |D2|-----| 7|Jump on No Carry |If CY=0(10~s)|

|JNZ a |C2|-----| 7|Jump on No Zero |If Z=0 (10~s)|

|JP a |F2|-----| 7|Jump on Plus |If S=0 (10~s)|

|JPE a |EA|-----| 7|Jump on Parity Even |If P=1 (10~s)|

|JPO a |E2|-----| 7|Jump on Parity Odd |If P=0 (10~s)|

|JZ a |CA|-----| 7|Jump on Zero |If Z=1 (10~s)|

|LDA a |3A|-----|13|Load Accumulator direct |A=[a] |

|LDAX B |0A|-----| 7|Load Accumulator indirect |A=[BC] |

|LDAX D |1A|-----| 7|Load Accumulator indirect |A=[DE] |

|LHLD a |2A|-----|16|Load HL Direct |HL=[a] |

|LXI B,nn |01|-----|10|Load Immediate BC |BC=nn |

|LXI D,nn |11|-----|10|Load Immediate DE |DE=nn |

|LXI H,nn |21|-----|10|Load Immediate HL |HL=nn |

|LXI SP,nn|31|-----|10|Load Immediate Stack Ptr |SP=nn |

|MOV r1,r2|7F|-----| 4|Move register to register |r1=r2 (1XX)|

|MOV M,r |77|-----| 7|Move register to Memory |[HL]=r (16X)|

|MOV r,M |7E|-----| 7|Move Memory to register |r=[HL] (1X6)|

|MVI r,n |3E|-----| 7|Move Immediate |r=n (0X6)|

|MVI M,n |36|-----|10|Move Immediate to Memory |[HL]=n |

|NOP |00|-----| 4|No Operation | |

|ORA r |B7|**0*0| 4|Inclusive OR Accumulator |A=Avr (26X)|

|ORA M |B6|**0*0| 7|Inclusive OR Accumulator |A=Av[HL] |

|ORI n |F6|**0*0| 7|Inclusive OR Immediate |A=Avn |

|OUT p |D3|-----|10|Output |[p]=A |

|PCHL |E9|-----| 6|Jump HL indirect |PC=[HL] |

|POP B |C1|-----|10|Pop BC |BC=[SP]+ |

|POP D |D1|-----|10|Pop DE |DE=[SP]+ |

|POP H |E1|-----|10|Pop HL |HL=[SP]+ |

|SUB r |97|*****| 4|Subtract |A=A-r (22X)|

|SUB M |96|*****| 7|Subtract Memory |A=A-[HL] |

|SUI n |D6|*****| 7|Subtract Immediate |A=A-n |

|XRA r |AF|**0*0| 4|Exclusive OR Accumulator |A=Axr (25X)|

|XRA M |AE|**0*0| 7|Exclusive OR Accumulator |A=Ax[HL] |

|XRI n |EE|**0*0| 7|Exclusive OR Immediate |A=Axn |

|XTHL |E3|-----|16|Exchange stack Top with HL|[SP]<->HL

|SBB r |9F|*****| 4|Subtract with Borrow |A=A-r-CY |

|SBB M |9E|*****| 7|Subtract with Borrow |A=A-[HL]-CY |

|SBI n |DE|*****| 7|Subtract with Borrow Immed|A=A-n-CY

its a record register with whole lot detail of the instrument or commodity bought, in regard to managing details of the purchase of the instruments, its billing detail, type, number of instrument, expiry date (if any), signature etc. that is to be maintained by the administration

Exclusive OR with Accumulator.

The results are then placed in the accumulator.

This is quite a long story. The very 1st computer was invented during the reign of Henry the 8th.One of his exectioners was killed when the huge pc ran out of power(in the form of a cow turning a turbine). He vowed to get revenge so he invented in Heaven a complicated system on all modern PC's. When the fetch the execute cycle comes on, you should see a man with an axe cycling with his faithful pet cow called Bob. He will chop youir files into two sections. By the way this complete story is fictionous and i hope i kept you entertained.

difference between micro operation and microinstruction

Multiplexing of the data and address buses is done to reduce the pin count on the microprocessor chip. The address information is emitted at the beginning of a memory cycle, and external logic is expected to latch that address. Then the bus becomes the data bus and the required data is transferred to or from memory using the latched address.

In the 8085, this saves 8 pins at the cost of 1 pin, ALE. In the 8086/8088, this saves 16 pins at the cost of 1 pin, ALE. In some architectures or modes, there is no ALE, but the external logic is still required to know when to latch the address based on some other criteria.

As an example of that, in the original Intel 4004, the microprocessor's bus was 4 bits, while the address bus was 12 bits. There were 8 clock cycles. In the first three, external logic was expected to latch the three 4 bit parts of the 12 bit address. Similarly, in the next two, the resultant opcode, which as 8 bits, was multiplexed by the external logic into two 4 bit parts. (The 4004 was only a 16 pin chip, but it packed a lot of complexity in its day, being the world's first microprocessor.)

In many engineering schools the 8085 processor is used in introductory microprocessor courses. Trainer kits composed of a printed circuit board, 8085, and supporting hardware are offered by various companies. These kits usually include complete documentation allowing a student to go from solder to assembly language programming in a single course..

Many repeated consonant sounds placed near one another

Well, usually a registration is above the login thing on the website. But there's a catch to it. Its almost always closed and I really want to register. The admins wish they could fix it, but if they did, feralheart would just run slower. *sigh* I've downloaded the game and all and I want to register too. Just keep a close eye on the register. Anyways, hoped this helped, your not alone! ;)

In 8085 general purpose registers are used to hold data like any other registers.

In 8085 there are six types of special registers called general purpose registers.

The general purpose registers in 8085 are B, C, D, E, H and L.

Each register can hold 8 bit data. Apart from above functions these registers can also be used to work in pairs to hold 16 bit data.

They can work in pairs such as B-C, D-E, H-L to store 16 bit data.

The H-L pair work as a memory pointer.

A memory pointer holds the address of a particular memory location. They can store 16 bit address as they work in pairs.

There is no single instruction in the 8085 that would set bit 3 at address 25H. One way to do this would be...

PUSH F
LDA 25H
ORI 8H
STA 25H
POP F

The PUSH/POP pair could be eliminated if you did not want to save the accumulator and flags.

The 8086 has 16 bit data bus; the 8088 has an 8 bit data bus. The 8086 has a 6 byte instruction queue, and the 8088 has a 4 byte queue. The 8088 was the chip used in the first IBM PC; the 8086 wasn't used until later models. Since they share the exact same instruction set, which is referred to as the "x86 instruction set" these days, this is often confused. 8085 is a 8 bit processor,number of flags are 5 and memory capacity is 64KB while 8086 is a 16 bit processor ,number of flags are 9 and memory capacity is 1 MB.The main difference between 8085 and 8086 is that 8086 uses pipelining. The 8086/8088 microprocessor is a 16 bt computer, with a 20 bit address bus using a segmented memory architecture. The execution unit architecture, registers, instructions, etc. in both is the same. The bus interface unit on the 8086 is 16 bits wide, where on the 8088 it is 8 bits wide.

SVC (supervisor-call): A request from the user-program to the kernel (or supervisor), to do something like open a file, allocate memory, create a new process etc.

In x86 platform SVCs are executed via "INT nn" machine instruction, that's what Intel calls 'software interrupt'.