Intel 8085

Control Flag Register:

The Control Flag Register (CFR), also known as the Program Status Word (PSW), is a register used to control the execution flow and behavior of the processor. It typically stores various control flags that govern different aspects of the CPU's operation. Some common flags found in the Control Flag Register include:

Carry Flag (CF): Used to indicate whether an arithmetic operation generated a carry or borrow.

Zero Flag (ZF): Indicates whether the result of an operation is zero.

Sign Flag (SF): Indicates the sign (positive or negative) of the result.

Overflow Flag (OF): Indicates whether an arithmetic operation resulted in an overflow.

Interrupt Flag (IF): Determines whether interrupts are enabled or disabled.

The Control Flag Register provides control over program execution, including branching, interrupt handling, and arithmetic operations. It helps determine the outcome of operations and can be used for conditional branching based on specific flag states.

Conditional Flag Register:

The Conditional Flag Register (CFR), also known as the Condition Code Register (CCR) or Status Register (SR), contains flags that reflect the result of the most recent arithmetic or logical operation performed by the processor. These flags are used to perform conditional branching and control the flow of instructions based on specific conditions.

The flags present in the Conditional Flag Register can vary depending on the processor architecture, but some common flags include:

Zero Flag (ZF): Indicates whether the result of an operation is zero.

Sign Flag (SF): Indicates the sign (positive or negative) of the result.

Overflow Flag (OF): Indicates whether an arithmetic operation resulted in an overflow.

Carry Flag (CF): Used to indicate whether an arithmetic operation generated a carry or borrow.

Auxiliary Carry Flag (AF): Indicates a carry or borrow from the lower-order nibble (4 bits) to the higher-order nibble.

The Conditional Flag Register is primarily used for conditional jumps or branches, allowing the processor to alter the program flow based on the current flag states.

To summarize, the Control Flag Register focuses on controlling the processor's behavior and handling interrupts, while the Conditional Flag Register reflects the outcome of arithmetic and logical operations and enables conditional branching based on flag states.

As quoted from Google Books, "Word size refers to the number of bits that a microprocessor can manipulate at one time."

The instruction opcode is a type of data contained in memory, pointed to by the PC (Program Counter) register.

Data rate

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Interrupts are required in order to get the attention of the CPU. A CPU typically has two interrupt lines. One is the nonmaskable interrupt line (NMI). That is used in the case of critical errors, since this interrupt cannot be ignored. The other one is the regular interrupt line. That is used by hardware devices and certain software to get the attention of the CPU. When you move a mouse, for instance, that creates both a hardware and software interrupt. So the CPU would then process the mouse driver code and move the cursor, then get back to what it was doing.

we have 8 s/w interrupts from rst0 to rst7. and rst5.5,6.5 comes in between (rst5 and rst6) and (rst6 and rst7) respectively. like that we get rst7.5.. but i m not sure

loop: mvi c,59

dcr c

mov a,c

daa

movc,a

jnz loop

end

In the 8085, six registers (B, C, D, E, F, H, and L) can be used as individual 8-bit registers, or paired up and treated as 16-bit registers. The pairs are BC, DE, and HL.

The universal shift register is a type of sequential logic circuit that is used for the storage or transfer of data in the form of binary numbers and then "shifts" the data out once every clock cycle.

Three for opcode fetch, one for decode, two to process the manipulation of the stack pointer.

The 8085 was replaced with the 8086/8088. As such, there is no 16 bit version of the 8085.

zero

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In the 8085, if the accumulator starts as 00H, then adding 89H and 79H to it results in a value of 02H with CARRY set.

The POP H instruction in the 8085 copies the top of stack to the HL register and then increments the stack pointer by 2. In C pseudo code, the sequence is L = *(SP++); H = *(SP++);

800ns

The capacity of a register refers to the amount of data it can hold, typically measured in bits or bytes. It determines how many binary values can be stored and processed at one time. For example, a 32-bit register can hold 32 bits of information, allowing it to represent 2^32 different values. The register's capacity is crucial in computing as it influences the performance and efficiency of data processing tasks.

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20H

the opcode is fetched from the memory and decoded

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It depends on the CPU architecture. Most modern CPUs support several levels of interrupts ranging from high priority to low. If the first interrupt that occurred was a high priority, then a lower priority one occurs, the high priority will continue to execute until it is done, then the the CPU will immediately jump to the lower one. Conversely, if the lower priority interrupt occurred first, it will be interrupted until the higher interrupt is serviced.

For 80x86 series processors, do not confuse priority with vector. You may remember in the older days interrupt 13 belonging to the hard drive, and interrupts 3 and 4 being part of the serial port. This is not a function of the CPU but of the interrupt controller. The function of this device is beyond the scope of my answer here. 80x86 has 2 interrupt sources: maskable and non-maksable. Think of the non-maskable as the higher priority and the maskable as the lower. Most peripherals use the maskable interrupt line. Although a few, often functions of the BIOS, Fault, or Paged/Protected mode make use of the non-masked interrupt.