Microprocessors

Core capabilities are those skills that differentiate the manufacturing from its competitors

TTL

offset storage for forming physical address

Intel Core Duo

Intel Core 2 Duo Intel Core 2 Quad Intel Celeron AMD Athlon XP

AMD Phenom X2

And two for laptops:

Intel Atom

AMD Turion X2

It's impossible :o) You can disable and enable any interrupt source by setting or clearing corresponding bit in proper control register. Show me your code - we will see what can be done wrong.

Asar

fotousa@interia.pl

You can set bit I on SREG by 1 to enable global interrupt or by 0 to disable it.

in c programming you can write

#asm ("sei") //to enable global interupt

#asm ("cli") //to disable global interupt

M. Wicaksono A.

It buffers and routes data from source to another It buffers and routes data from source to another

Cache is a high speed memory which is basically used for the following reason:

As the speed of the main memory is not as much as the speed of the CPU.so just to compensate the speed mistmatch between the CPU and main memory the cache is used in between the two.so whenever the CPU asks for any data its being checked with the cache memory and if present then "cache hit" occurs or else "cache miss" occurs wher the CPU takes the data form the main memory and that data's cpoy is being send to the cache for any further operation where the CPU can request for the same data.

Anand bhat(mca@kiit-870024)

Yes.

Bigger number = better.

Data segment

msg1 db 10,13,'enter the string: $'

msg2 db 10,13,'string is palindrome$'

msg3 db 10,13,'string is not palindrome$'

new db 10,13,'$'

inst db 20 dup(0)

data ends

code segment

assume cs:code,ds:data

start:

mov ax,data

mov ds,ax

lea dx,msg1

mov ah,09h

int 21h

mov bx,00

up:

mov ah,01h

int 21h

cmp al,0dh

je down

mov [inst+bx],al

inc bx

loop up

down:

mov di,0

dec bx

jnz check

check:

mov al,[inst+bx]

cmp al,[inst+di]

jne fail

inc di

dec bx

jnz check

lea dx,new

mov ah,09h

int 21h

lea dx,msg2

mov ah,09h

int 21h

jmp finish

fail:

lea dx,msg3

mov ah,09h

int 21h

finish:

int 3

code ends

end start

end

Complex programmable logic device (CPLD) are programmable digital logic devices which are simpler and lesser capacity than FPGA (Field Programmable Gate Arrays) devices. CPLDs have a non-volatile memory (i.e. turning off the power does not require reprogramming of CPLD)

Microcontrollers (uP or MCU) are small and cost effective but self contained computer chips (compared to general purpose processor chips used in personal computers) used for embedded applications in industrial, consumer electronics products and automobiles. Microcontrollers may or may not have inbuilt memory.

CPLDs are used for implementing logic but they do not have a embedded processor like in microcontrollers.

- Neeraj Sharma

1024

All micro-controllers are going to be difficult to use, because you build your circuits around them, not vice versa. From a programmer perspective, the BASIC Stamp uses PBasic which is very easy to use and understand. The PIC16F84 Micro series uses assembly, but only has 30 commands and is much more powerful IMHO.

Dildo's...S......So many Dildo's

0.8330078125 mb (853/1024)

just a note: Clarify your question

Bit-addressable registers are registers that its bits can be modified individually. that means if you have register named "ACC" that is bit addressable , you can change its bits (D0 -D7) individually by special instructions SETB and CLR.

ex: SETB ACC.3 ; will set bit number 4 (remember bit 0) in the register

in 8051 there are many bit-addressable registers such as A (ACC), B, SCON, PCON, TCON, p0,p1,p2,p3 .

best wishes,

drdigital.

.44*1024=450.56kb

A7a

Apple computer

faster operation

There are a lot of great sites that give great electronic deals. Definitely check out Amazon and their Deals of the Day. You may also want to check out, Brandsmart USA, Best Buy, Newegg, and Microcenter.

6m 24s

You Have 1024 Kb's In A Mb. So Take 1024 x 15, Since The File Is 15 Mb, Instead Of 1 Mb. You Will Get 15,360. Then You Take That Divided By 40 To See How Many Seconds It Will Take To Download The File, Which Will Give You 384. 384s In Turn Is 6m 24s For The File To Download.

Two typical components of a CPU are:

The arithmetic logic unit (ALU), which performs arithmetic and logical operations.

The control unit (CU), which extracts instructions from memory and decodes and executes them, calling on the ALU when necessary.

Additional time required because of a miss it is generally the 30~40 cycles for Main Memory.

Because it is 8- 8-bit controller (8000 series)

5- It has 5 interrupts

1- It has only one serial communication port

Incorrect. Fetching and decoding of any instruction takes a minimum of four clock cycles in the 8085.

T1 = ALE and address emission

T2 = Read initiation

T3 = Read completion

T4 = Opcode decode

T1, T2, and T3 are repeated for each additional byte of the instruction. In all cases, Twait, if indicated by not READY, is inserted between T2 and T3.